CY7C68300C-56PVXC Cypress Semiconductor Corp, CY7C68300C-56PVXC Datasheet - Page 40
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CY7C68300C-56PVXC
Manufacturer Part Number
CY7C68300C-56PVXC
Description
IC USB 2.0 BRIDGE AT2LP 56-SSOP
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Type
USB to ATA/ATAPI Bridger
Datasheets
1.CY7C68300C-56PVXC.pdf
(42 pages)
2.CY7C68320C-100AXA.pdf
(44 pages)
3.CY7C68300C-56PVXC.pdf
(42 pages)
Specifications of CY7C68300C-56PVXC
Package / Case
56-SSOP
Controller Type
USB 2.0 Controller
Interface
I²C
Voltage - Supply
3.15 V ~ 3.45 V
Current - Supply
50mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Number Of Bits
48
Operating Temperature Range
0 C to + 70 C
Supply Current
10 mA
Operating Supply Voltage
3.3 V
Controller Family/series
(8051) USB
Core Size
8 Bit
No. Of I/o's
6
Embedded Interface Type
I2C, USB
Digital Ic Case Style
SSOP
Supply Voltage Range
3V To 3.6V
Rohs Compliant
Yes
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Operating Temperature (max)
70C
Package Type
SSOP
Rad Hardened
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY4615B - KIT USB TO ATA REFERENCE DESIGN
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-2266-5
CY7C68300C-56PVXC
CY7C68300C-56PVXC
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C68300C-56PVXC
Manufacturer:
HITACHI
Quantity:
2 000
Company:
Part Number:
CY7C68300C-56PVXC
Manufacturer:
CY
Quantity:
8
Part Number:
CY7C68300C-56PVXC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
General PCB Layout Recommendations for
USB Mass Storage Designs
The following recommendations must be followed to ensure
reliable high performance operation:
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Document Number: 001-05809 Rev. *H
Use at least a four-layer, impedance controlled board to
maintain signal quality.
Specify specific impedance targets (ask your board vendor
what they can achieve).
Maintain uniform trace widths and trace spacing to control
impedance.
Minimize reflected signals by avoiding using stubs and vias.
Connect the USB connector shell and signal ground as near to
the USB connector as possible.
Use bypass or flyback capacitors on VBUS near the connector.
Keep DPLUS and DMINUS trace lengths to within 2 mm of
each other in length, with a preferred length of 20 to 30 mm.
Maintain a solid ground plane under the DPLUS and DMINUS
traces. Do not allow the plane to be split under these traces.
Do not place vias on the DPLUS or DMINUS trace routing for
a more stable design.
Figure 14. 56-pin QFN (8 × 8 × 0.9 mm) - Sawn
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Source for recommendations:
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Quad Flat Package No Leads (QFN) Package
Design Notes
Electrical contact of the part to the Printed Circuit Board (PCB)
is made by soldering the leads on the bottom surface of the
package to the PCB. Hence, special attention is required to the
heat transfer area below the package to provide a good thermal
bond to the circuit board. A Copper (Cu) fill must be designed
into the PCB as a thermal pad under the package. Heat is
transferred from the AT2LP through the device’s metal paddle on
the bottom side of the package. Heat from here is conducted to
the PCB at the thermal pad. It is then conducted from the thermal
pad to the PCB inner ground plane by a 5 × 5 array of vias. A via
is a plated through-hole in the PCB with a finished diameter of
13 mil. The QFN’s metal die paddle must be soldered to the
PCB’s thermal pad. Solder mask is placed on the board top side
over each via to resist solder flow into the via. The mask on the
top side also minimizes outgassing during the solder reflow
process.
Isolate the DPLUS and DMINUS traces from all other signal
traces by no less than 10 mm.
EZ-USB FX2LP PCB Design Recommendations
www.cypress.com/?docID=4696
High-Speed USB Platform Design Guidelines
http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf
CY7C68300C, CY7C68301C
CY7C68320C, CY7C68321C
001-53450 *B
Page 40 of 44
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