CY7C68300C-56PVXC Cypress Semiconductor Corp, CY7C68300C-56PVXC Datasheet - Page 14

• Manufacturer Part Number: CY7C68300C-56PVXC
• Description: IC USB 2.0 BRIDGE AT2LP 56-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: USB to ATA/ATAPI Bridger

Specifications of CY7C68300C-56PVXC

• Package / Case: 56-SSOP
• Controller Type: USB 2.0 Controller
• Interface: I²C
• Voltage - Supply: 3.15 V ~ 3.45 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Bits: 48
• Operating Temperature Range: 0 C to + 70 C
• Supply Current: 10 mA
• Operating Supply Voltage: 3.3 V
• Controller Family/series: (8051) USB
• Core Size: 8 Bit
• No. Of I/o's: 6
• Embedded Interface Type: I2C, USB
• Digital Ic Case Style: SSOP
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: SSOP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4615B - KIT USB TO ATA REFERENCE DESIGN
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2266-5; CY7C68300C-56PVXC

DRVPWRVLD
When this pin is enabled with bit 0 of configuration address 0x08
(DRVPWRVLD Enable), the AT2LP informs the host that a
removable device, such as a CF card, is present. The AT2LP
uses DRVPWRVLD to detect that the removable device is
present. Pin polarity is controlled by bit 1 of configuration
address 0x08. When DRVPWRVLD is deasserted, the AT2LP
reports a “no media present” status (ASC = 0x3A, ASQ = 0x00)
when queried by the host. When the media is detected again, the
AT2LP reports a “media changed” status to the host
(ASC = 0x28, ASQ = 0x00) when queried.
When a removable device is used, it is always considered by the
AT2LP to be the IDE master device. Only one removable device
may be attached to the AT2LP. If the system only contains a
removable device, bit 6 of configuration address 0x08 (Search
ATA Bus) must be set to ‘0’ to disable ATA device detection at
startup. If a non-removable device is connected in addition to a
removable media device, the non removable device must be
configured as IDE slave (device address 1).
Document Number: 001-05809 Rev. *H
NAK Request
No
Return Interrupt Data
Set Int_Data = 0
USB Interrupt
Int_Data = 1?
Pipe Polled?
Yes
Yes
Figure 7. SYSIRQ Latching Algorithm
No
GPIO Pins
The GPIO pins enable a general purpose input and output
interface. There are several different interfaces to the GPIO pins:
■
■
■
LOWPWR#
LOWPWR# is an output pin that is driven to ‘0’ when the AT2LP
is not in suspend. LOWPWR# is placed in High Z when the
AT2LP is in a suspend state. This pin only indicates the state of
the AT2LP and must not be used to determine the status of the
USB host because of variations in the behavior of different hosts.
Configuration bytes 0x09 and 0x0A contain the default settings
for the GPIO pins upon initial AT2LP configuration.
The host can modify the settings of the GPIO pins during
operation. This is done with vendor-specific commands
described in
The status of the GPIO pins is returned on the interrupt endpoint
(EP1) in response to a SYSIRQ. See
SYSIRQ details.
Yes
No
Programming the EEPROM on page
CY7C68300C, CY7C68301C
CY7C68320C, CY7C68321C
Latch State of IO Pins
Set Int_Data = 1
SYSIRQ=1?
Int_Data = 0
SYSIRQ=0?
Yes
and
SYSIRQ on page 13
No
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