CY7C68300C-56PVXC Cypress Semiconductor Corp, CY7C68300C-56PVXC Datasheet - Page 11

• Manufacturer Part Number: CY7C68300C-56PVXC
• Description: IC USB 2.0 BRIDGE AT2LP 56-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: USB to ATA/ATAPI Bridger

Specifications of CY7C68300C-56PVXC

• Package / Case: 56-SSOP
• Controller Type: USB 2.0 Controller
• Interface: I²C
• Voltage - Supply: 3.15 V ~ 3.45 V
• Current - Supply: 50mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Bits: 48
• Operating Temperature Range: 0 C to + 70 C
• Supply Current: 10 mA
• Operating Supply Voltage: 3.3 V
• Controller Family/series: (8051) USB
• Core Size: 8 Bit
• No. Of I/o's: 6
• Embedded Interface Type: I2C, USB
• Digital Ic Case Style: SSOP
• Supply Voltage Range: 3V To 3.6V
• Rohs Compliant: Yes
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Package Type: SSOP
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY4615B - KIT USB TO ATA REFERENCE DESIGN
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2266-5; CY7C68300C-56PVXC

Table 1. AT2LP Pin Descriptions (continued)
Note Italic pin names denote pin functionality during CY7C68300A compatibility mode
Document Number: 001-05809 Rev. *H
Notes
TQFP
6. If byte 8, bit 4 of the EEPROM is set to ‘0’, the ATA interface pins are only active when VBUS_ATA_EN is asserted. See
7. The General Purpose inputs can be enabled on ATAPUEN, PWR500#, and DRVPWRVLD via EEPROM byte 8, bit 7 on CY7C68320C/CY7C68321C.
70
100
67
68
69
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
[7]
QFN
36
36
13
54
N/A
N/A
N/A
N/A
N/A
56
33
34
35
37
38
39
40
41
42
43
44
45
46
47
48
[7]
[7]
[7]
[7]
SSOP
N/A
N/A
N/A
N/A
N/A
N/A
56
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
(VBUS_PWR_VALID)
VBUS_ATA_ENABLE
DRVPWRVLD
Pin Name
ARESET#
(ATA_EN)
RESET#
INTRQ
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
(DA2)
CS0#
CS1#
DD10
DD11
GND
GND
GND
DA0
DA1
DA2
DD8
DD9
V
V
NC
NC
CC
CC
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
Type
GND
PWR
I/O
I/O
I/O
I/O
PWR
I/O
GND
Pin
NC
NC
I
[6]
I
I
I
[6]
[6]
[6]
[6]
[7]
[6]
[6]
[6]
[6]
[6]
[6]
Default State
Driven HIGH
Driven HIGH
Driven HIGH
Driven HIGH
Driven HIGH
at Startup
after 2 ms
after 2 ms
after 2 ms
after 2 ms
after 2 ms
High Z
High Z
High Z
High Z
delay
delay
delay
delay
delay
Input
Input
Input
Input
ATA interrupt request.
ATA address.
ATA address.
Device presence detect. (See
Configurable logical polarity is controlled by EEPROM address
0x08. This pin must be pulled HIGH if functionality is not used.
Alternate function. Input when the EEPROM configuration
byte 8 has bit 7 set to ‘1’. The input value is reported through
EP1IN (byte 0, bit 0).
ATA chip select.
ATA chip select.
ATA address.
ATA reset.
Ground.
No connect.
Chip reset (See
V
VBUS detection (See
ATA data bit 8.
ATA data bit 9.
ATA data bit 10.
ATA data bit 11.
Ground.
V
No connect.
General Purpose I/O pins (See
GPIO pins must be tied to GND if functionality is not used.
Ground.
CC
CC
. Connect to 3.3 V power source.
. Connect to 3.3 V power source.
CY7C68300C, CY7C68301C
CY7C68320C, CY7C68321C
RESET# on page
Pin Description
VBUS_ATA_ENABLE on page
VBUS_ATA_ENABLE on page
DRVPWRVLD on page
GPIO Pins on page
15).
Page 11 of 44
15.
14). The
15).
14).
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