MCP2515-I/SO Microchip Technology, MCP2515-I/SO Datasheet - Page 41

• Manufacturer Part Number: MCP2515-I/SO
• Description: IC CAN CONTROLLER W/SPI 18SOIC
• Manufacturer: Microchip Technology

Specifications of MCP2515-I/SO

• Package / Case: 18-SOIC (7.5mm Width)
• Controller Type: CAN Interface
• Interface: SPI
• Voltage - Supply: 2.7 V ~ 5.5 V
• Current - Supply: 10mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Product: Controller Area Network (CAN)
• Number Of Transceivers: 1
• Data Rate: 1 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Supply Current (max): 10 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage Range: 2.7V To 5.5V
• Driver Case Style: SOIC
• No. Of Pins: 18
• Operating Temperature Range: -40°C To +85°C
• Filter Terminals: SMD
• Supply Voltage Min: 2.7V
• Rohs Compliant: Yes
• Clock Frequency: 40MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MCP2515DM-BM - BOARD DEMO FOR MCP2515/51MCP2515DM-PTPLS - BOARD DAUGHTER PICTAIL MCP2515MCP2515DM-PCTL - BOARD DEMO FOR MCP2515DV251001 - KIT DEVELOPMENT CAN MCP2510
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.3
Some requirements for programming of the time
segments:
• PropSeg + PS1 >= PS2
• PropSeg + PS1 >= T
• PS2 > SJW
For example, assuming that a 125 kHz CAN baud rate
with F
T
T
T
Typically, the sampling of the bit should take place at
about 60-70% of the bit time, depending on the system
parameters. Also, typically, the T
SyncSeg = 1 T
PS1 = 7 T
transition. This would leave 6 T
Since PS2 is 6, according to the rules, SJW could be a
maximum of 4 T
only necessary when the clock generation of the differ-
ent nodes is inaccurate or unstable, such as using
ceramic resonators. So a SJW of 1 is usually enough.
5.4
The bit timing requirements allow ceramic resonators
to be used in applications with transmission rates of up
to 125 kbit/sec as a rule of thumb. For the full bus
speed range of the CAN protocol, a quartz oscillator is
required. A maximum node-to-node oscillator variation
of 1.7% is allowed.
© 2010 Microchip Technology Inc.
OSC
Q
Q
.
= 500 ns. To obtain 125 kHz, the bit time must be 16
OSC
= 50 ns, choose BRP<5:0> = 04h, then
Programming Time Segments
Oscillator Tolerance
Q
= 20 MHz is desired:
would place the sample at 10 T
Q
Q
. However, a large SJW is typically
and PropSeg = 2 T
DELAY
Q
for PS2.
DELAY
is 1-2 T
Q
. So setting
Q
after the
Q
.
5.5
The configuration registers (CNF1, CNF2, CNF3)
control the bit timing for the CAN bus interface. These
registers can only be modified when the MCP2515 is in
Configuration mode (see Section 10.0 “Modes of
Operation”).
5.5.1
The BRP<5:0> bits control the baud rate prescaler.
These bits set the length of T
input frequency, with the minimum T
2 T
SJW<1:0> bits select the SJW in terms of number of
T
5.5.2
The PRSEG<2:0> bits set the length (in T
propagation segment. The PHSEG1<2:0> bits set the
length (in T
The SAM bit controls how many times the RXCAN pin
is sampled. Setting this bit to a ‘1’ causes the bus to be
sampled three times: twice at T
point and once at the normal sample point (which is at
the end of PS1). The value of the bus is determined to
be the majority sampled. If the SAM bit is set to a ‘0’,
the RXCAN pin is sampled only once at the sample
point.
The BTLMODE bit controls how the length of PS2 is
determined. If this bit is set to a ‘1’, the length of PS2 is
determined by the PHSEG2<2:0> bits of CNF3 (see
Section 5.5.3 “CNF3”). If the BTLMODE bit is set to a
‘0’, the length of PS2 is greater than that of PS1 and the
information processing time (which is fixed at 2 T
the MCP2515).
5.5.3
The PHSEG2<2:0> bits set the length (in T
if the CNF2.BTLMODE bit is set to a ‘1’. If the
BTLMODE bit is set to a ‘0’, the PHSEG2<2:0> bits
have no effect.
Q
s.
OSC
Bit Timing Configuration
Registers
(when
Q
CNF1
CNF2
CNF3
’s) of PS1.
BRP<5:0>
MCP2515
Q
=
Q
relative to the OSC1
/2 before the sample
‘b000000’).
DS21801F-page 41
Q
length being
Q
Q
’s) of PS2,
’s) of the
Q
The
for