MCP2515-I/SO Microchip Technology, MCP2515-I/SO Datasheet

IC CAN CONTROLLER W/SPI 18SOIC

MCP2515-I/SO

Manufacturer Part Number
MCP2515-I/SO
Description
IC CAN CONTROLLER W/SPI 18SOIC
Manufacturer
Microchip Technology
Datasheets

Specifications of MCP2515-I/SO

Package / Case
18-SOIC (7.5mm Width)
Controller Type
CAN Interface
Interface
SPI
Voltage - Supply
2.7 V ~ 5.5 V
Current - Supply
10mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Product
Controller Area Network (CAN)
Number Of Transceivers
1
Data Rate
1 Mbps
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Supply Current (max)
10 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage Range
2.7V To 5.5V
Driver Case Style
SOIC
No. Of Pins
18
Operating Temperature Range
-40°C To +85°C
Filter Terminals
SMD
Supply Voltage Min
2.7V
Rohs Compliant
Yes
Clock Frequency
40MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MCP2515DM-BM - BOARD DEMO FOR MCP2515/51MCP2515DM-PTPLS - BOARD DAUGHTER PICTAIL MCP2515MCP2515DM-PCTL - BOARD DEMO FOR MCP2515DV251001 - KIT DEVELOPMENT CAN MCP2510
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Features
• Implements CAN V2.0B at 1 Mb/s:
• Receive buffers, masks and filters:
• Data byte filtering on the first two data bytes
• Three transmit buffers with prioritization and abort
• High-speed SPI Interface (10 MHz):
• One-shot mode ensures message transmission is
• Clock out pin with programmable prescaler:
• Start-of-Frame (SOF) signal is available for
• Interrupt output pin with selectable enables
• Buffer Full output pins configurable as:
• Request-to-Send (RTS) input pins individually
• Low-power CMOS technology:
• Temperature ranges supported:
© 2010 Microchip Technology Inc.
- 0 – 8 byte length in the data field
- Standard and extended data and remote
- Two receive buffers with prioritized message
- Six 29-bit filters
- Two 29-bit masks
(applies to standard data frames)
features
- SPI modes 0,0 and 1,1
attempted only one time
- Can be used as a clock source for other
monitoring the SOF signal:
- Can be used for time-slot-based protocols
- Interrupt output for each receive buffer
- General purpose output
configurable as:
- Control pins to request transmission for each
- General purpose inputs
- Operates from 2.7V – 5.5V
- 5 mA active current (typical)
- 1 µA standby current (typical) (Sleep mode)
- Industrial (I): -40°C to +85°C
- Extended (E): -40°C to +125°C
frames
storage
device(s)
and/or bus diagnostics to detect early bus
degredation
transmit buffer
Stand-Alone CAN Controller With SPI Interface
Description
Microchip Technology’s MCP2515 is a stand-alone
Controller
implements the CAN specification, version 2.0B. It is
capable of transmitting and receiving both standard
and extended data and remote frames. The MCP2515
has two acceptance masks and six acceptance filters
that are used to filter out unwanted messages, thereby
reducing the host MCUs overhead. The MCP2515
interfaces with microcontrollers (MCUs) via an industry
standard Serial Peripheral Interface (SPI).
Package Types
18-Lead PDIP/SOIC
20-LEAD TSSOP
* Includes Exposed Thermal
Pad (EP); see
20-Lead 4x4 QFN*
MCP2515
Area
MCP2515
Table
CLKOUT/SOF
CLKOUT/SOF
CLKOUT
TX0RTS
TX1RTS
TX2RTS
Network
1-1.
TX0RTS
TX1RTS
TX2RTS
TX0RTS
TX1RTS
TX2RTS
NC
RXCAN
RXCAN
TXCAN
TXCAN
OSC2
OSC1
OSC2
OSC1
V
Vss
1
2
3
4
5
NC
SS
20
6
(CAN)
10
5
6
7
8
9
1
2
3
4
1
2
3
4
5
6
7
8
9
19 18 17
7
EP
21
8
DS21801F-page 1
controller
9
16
10
18
17
16
15
14
13
12
10
20
19
18
17
16
15
14
13
12
11
11
15
14
13
12
11
V
RESET
CS
SO
SI
SCK
INT
RX0BF
RX1BF
V
RESET
CS
SO
SI
SCK
INT
RX0BF
RX1BF
NC
DD
SO
SI
NC
INT
DD
SCK
that

Related parts for MCP2515-I/SO

MCP2515-I/SO Summary of contents

Page 1

... CAN specification, version 2.0B capable of transmitting and receiving both standard and extended data and remote frames. The MCP2515 has two acceptance masks and six acceptance filters that are used to filter out unwanted messages, thereby reducing the host MCUs overhead. The MCP2515 interfaces with microcontrollers (MCUs) via an industry standard Serial Peripheral Interface (SPI) ...

Page 2

... MCP2515 NOTES: DS21801F-page 2 © 2010 Microchip Technology Inc. ...

Page 3

... Microchip Technology Inc. 1.2 Control Logic The control logic block controls the setup and operation of the MCP2515 by interfacing to the other blocks in order to pass information and control. Interrupt pins are provided to allow greater system flexibility. There is one multi-purpose interrupt pin (as ...

Page 4

... Chip select input pin for SPI interface I Active low device reset input P Positive supply for logic and I/O pins — No internal connection Node Controller SPI MCP2515 TX RX XCVR Alternate Pin Function — — Start-of-Frame signal General purpose digital input. 100 kΩ internal pull- General purpose digital input ...

Page 5

... Transmit/Receive Buffers/Masks/ Filters The MCP2515 has three transmit and two receive buffers, two acceptance masks (one for each receive buffer) and a total of six acceptance filters. shows a block diagram of these buffers and their connection to the protocol engine. FIGURE 1-3: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM ...

Page 6

... MCP2515 1.5 CAN Protocol Engine The CAN protocol engine combines several functional blocks, shown in Figure 1-4 and described below. 1.5.1 PROTOCOL FINITE STATE MACHINE The heart of the engine is the Finite State Machine (FSM). The FSM is a sequencer that controls the sequential data stream between the TX/RX shift register, the CRC register and the bus line ...

Page 7

... CAN MESSAGE FRAMES The MCP2515 supports standard data frames, extended data frames and remote frames (standard and extended), as defined in the CAN 2.0B specification. 2.1 Standard Data Frame The CAN standard data frame is shown in As with all other frames, the frame begins with a Start- Of-Frame (SOF) bit, which is of the dominant state and allows hard synchronization of all nodes ...

Page 8

... Note: Case 2 should never occur with the MCP2515 due to very short internal delays. 2.6 Interframe Space The interframe space separates a preceding frame (of any type) from a subsequent data or remote frame. ...

Page 9

... FIGURE 2-1: STANDARD DATA FRAME © 2010 Microchip Technology Inc. Del ACK Bit Slot Ack Del CRC DLC0 DLC3 RB0 Bit Reserved IDE RTR ID0 ID3 10 ID Start-of-Frame MCP2515 DS21801F-page 9 ...

Page 10

... MCP2515 FIGURE 2-2: EXTENDED DATA FRAME DS21801F-page 10 Del ACK Bit Slot Ack Del CRC DLC0 DLC3 RB0 bits Reserved RB1 RTR EID0 EID17 IDE SRR ID0 ID3 ID10 Start-Of-Frame © 2010 Microchip Technology Inc. ...

Page 11

... FIGURE 2-3: REMOTE FRAME © 2010 Microchip Technology Inc. Del ACK Bit Slot Ack Del CRC DLC0 DLC3 RB0 bits Reserved RB1 RTR EID0 EID17 IDE SRR ID0 ID3 ID10 Start-Of-Frame MCP2515 DS21801F-page 11 ...

Page 12

... MCP2515 FIGURE 2-4: ACTIVE ERROR FRAME Start-Of-Frame DS21801F-page 12 DLC0 DLC3 RB0 Bit Reserved IDE RTR ID0 ID3 10 ID © 2010 Microchip Technology Inc. ...

Page 13

... FIGURE 2-5: OVERLOAD FRAME © 2010 Microchip Technology Inc. Del ACK Bit Slot Ack Del CRC DLC0 DLC3 RB0 IDE RTR ID0 10 ID Start-Of-Frame MCP2515 DS21801F-page 13 ...

Page 14

... MCP2515 NOTES: DS21801F-page 14 © 2010 Microchip Technology Inc. ...

Page 15

... Transmit Priority Transmit priority is a prioritization within the MCP2515 of the pending transmittable messages. This is independent from, and not necessarily related to, any prioritization implicit in the message arbitration scheme built into the CAN protocol. ...

Page 16

... Configuration and control of these pins is accomplished using the TXRTSCTRL register (see Register 3-3). The TXRTSCTRL register can only be modified when the MCP2515 is in Configuration mode (see Section 10.0 “Modes of Operation”). If configured to operate as a request-to-send pin, the pin is mapped into the respective TXBnCTRL ...

Page 17

... CTRL.ABAT bit before the message has started transmission, will abort the message TXBnCTRL.TXREQ=0 or CANCTRL.ABAT=1 ? Yes Yes Message error Was No or Lost arbitration ? Lost Arbitration Set TxB CTRL.MLOA N No Set MCP2515 No Message Error Set TxBnCTRL.TXERR Yes CANINTE.MEERE? No Generate Interrupt Set CANTINF.MERRF DS21801F-page 17 ...

Page 18

... MCP2515 REGISTER 3-1: TXBnCTRL – TRANSMIT BUFFER n CONTROL REGISTER (ADDRESS: 30h, 40h, 50h) U-0 R-0 R-0 — ABTF MLOA bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 Unimplemented: Read as ‘0’ bit 6 ABTF: Message Aborted Flag bit ...

Page 19

... B0RTS B2RTSM U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-x R/W-x R/W-x SID7 SID6 SID5 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared MCP2515 R/W-0 R/W-0 B1RTSM B0RTSM bit Bit is unknown R/W-x R/W-x SID4 SID3 bit Bit is unknown ...

Page 20

... MCP2515 REGISTER 3-4: TXBnSIDL – TRANSMIT BUFFER n STANDARD IDENTIFIER LOW (ADDRESS: 32h, 42h, 52h) R/W-x R/W-x R/W-x SID2 SID1 SID0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 SID: Standard Identifier bits <2:0> bit 4 Unimplemented: Reads as ‘0’ ...

Page 21

... DLC3 DLC2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-x R/W-x R/W-x TXBnDm4 TXBnDm3 TXBnDm2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared MCP2515 R/W-x R/W-x DLC1 DLC0 bit Bit is unknown R/W-x R/W-x TXBnDm1 TXBnDm0 bit Bit is unknown ...

Page 22

... MCP2515 NOTES: DS21801F-page 22 © 2010 Microchip Technology Inc. ...

Page 23

... MESSAGE RECEPTION 4.1 Receive Message Buffering The MCP2515 includes two full receive buffers with multiple acceptance filters for each. There is also a separate Message Assembly Buffer (MAB) that acts as a third receive buffer (see Figure 4-2). 4.1.1 MESSAGE ASSEMBLY BUFFER Of the three receive buffers, the MAB is always committed to receiving the next message from the bus ...

Page 24

... MCP2515 4.3 Start-of-Frame Signal If enabled, the Start-Of-Frame signal is generated on the SOF pin at the beginning of each CAN message detected on the RXCAN pin. The RXCAN pin monitors an idle bus for a recessive- to-dominant edge. If the dominant condition remains until the sample point, the DSTEMP interprets this as a SOF and a SOF pulse is generated ...

Page 25

... Acceptance Filter Acceptance Mask Acceptance Filter RXM0 Acceptance Filter Acceptance Filter RXF0 Acceptance Filter Acceptance Filter RXF1 M Identifier A B Data Field MCP2515 CONFIGURING RXNBF PINS Pin Status Disabled, high-impedance X Receive buffer interrupt X Digital output = 0 0 Digital output = 1 1 RXM1 RXF2 RXF3 A ...

Page 26

... MCP2515 FIGURE 4-3: RECEIVE FLOW FLOWCHART Determines if the receive register is empty and able to accept a new message CANINTF.RX0IF = ? Yes Generate Overflow Error: Move message into RXB0 1 Set CANINTF.RX0IF = Set RXB0CTRL.FILHIT <0> according to which filter criteria Yes 1 CANINTE.RX0IE = ? No Are 1 BFPCTRL.B0BFM = Yes and 1 BF1CTRL.B0BFE = ...

Page 27

... BUKT: Rollover Enable bit 1 = RXB0 message will rollover and be written to RXB1 if RXB0 is full 0 = Rollover disabled bit 1 BUKT1: Read-only Copy of BUKT bit (used internally by the MCP2515) bit 0 FILHIT: Filter Hit bit - indicates which acceptance filter enabled reception of message 1 = Acceptance Filter 1 (RXF1 Acceptance Filter 0 (RXF0) ...

Page 28

... MCP2515 REGISTER 4-2: RXB1CTRL – RECEIVE BUFFER 1 CONTROL (ADDRESS: 70h) U-0 R/W-0 R/W-0 — RXM1 RXM0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 Unimplemented: Read as ‘0’ bit 6-5 RXM: Receive Buffer Operating Mode bits 11 = Turn mask/filters off ...

Page 29

... B1BFE B0BFE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R-x R-x R-x SID7 SID6 SID5 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared MCP2515 R/W-0 R/W-0 B1BFM B0BFM bit Bit is unknown R-x R-x SID4 SID3 bit Bit is unknown ...

Page 30

... MCP2515 REGISTER 4-5: RXBnSIDL – RECEIVE BUFFER n STANDARD IDENTIFIER LOW (ADDRESS: 62h, 72h) R-x R-x R-x SID2 SID1 SID0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 SID: Standard Identifier bits <2:0> These bits contain the three least significant bits of the Standard Identifier for the received message bit 4 SRR: Standard Frame Remote Transmit Request bit (valid only if IDE bit = ‘ ...

Page 31

... EID3 EID2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R-x R-x R-x RBnD4 RBnD3 RBnD2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared MCP2515 R-x R-x EID1 EID0 bit Bit is unknown R-x R-x EID1 EID0 bit Bit is unknown ...

Page 32

... If there is a match, that message will be loaded into the appropriate receive buffer. 4.5.1 DATA BYTE FILTERING When receiving standard data frames (11-bit identifier), the MCP2515 automatically applies 16 bits of masks and filters normally associated identifiers to the first 16 bits of the data field (data bytes 0 and 1) ...

Page 33

... RXB0 has a higher priority than RXB1. 4.5.5 CONFIGURING THE MASKS AND FILTERS The mask and filter registers can only be modified when the MCP2515 is in Configuration mode (see Section 10.0 “Modes of Operation”). Note: The mask and filter registers read all '0' when in any mode except Configuration mode ...

Page 34

... MCP2515 REGISTER 4-10: RXFnSIDH – FILTER n STANDARD IDENTIFIER HIGH (ADDRESS: 00h, 04h, 08h, 10h, 14h, 18h) R/W-x R/W-x R/W-x SID10 SID9 SID8 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 SID: Standard Identifier Filter bits <10:3> ...

Page 35

... EID3 EID2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 SID7 SID6 SID5 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared MCP2515 R/W-x R/W-x EID9 EID8 bit Bit is unknown R/W-x R/W-x EID1 EID0 bit Bit is unknown ...

Page 36

... MCP2515 REGISTER 4-15: RXMnSIDL – MASK n STANDARD IDENTIFIER LOW (ADDRESS: 21h, 25h) R/W-0 R/W-0 R/W-0 SID2 SID1 SID0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 SID: Standard Identifier Mask bits <2:0> These bits hold the mask bits to be applied to bits<2:0> of the Standard Identifier portion of a received ...

Page 37

... Digital Phase Lock Loop (DPLL) synchronization. The bit timing of the MCP2515 is implemented using a DPLL that is configured to synchronize to the incoming data, as well as provide the nominal timing for the transmitted data ...

Page 38

... MCP2515 PROPAGATION SEGMENT The Propagation Segment (PropSeg) exists to compensate for physical delays between nodes. The propagation delay is defined as twice the sum of the signal’s propagation time on the bus line, including the delays associated with the bus driver. The PropSeg is programmable from 1 – 8 TQ. ...

Page 39

... A transmitting node will not resynchronize on a positive phase error (e > 0 the absolute magnitude of the phase error is greater than the SJW, the appropriate phase segment will adjust by an amount equal to the SJW. MCP2515 DS21801F-page 39 ...

Page 40

... MCP2515 FIGURE 5-3: SYNCHRONIZING THE BIT TIME Input Signal ( PropSeg SyncSeg SJW (PS1) Input Signal (e > 0) SyncSeg PropSeg SJW (PS1) Resynchronization to a Slower Transmitter (e > 0) Input Signal (e < 0) SyncSeg PropSeg SJW (PS1) Resynchronization to a Faster Transmitter (e < 0) DS21801F-page 40 PhaseSeg1 (PS1) Sample ...

Page 41

... Bit Timing Configuration Registers The configuration registers (CNF1, CNF2, CNF3) control the bit timing for the CAN bus interface. These registers can only be modified when the MCP2515 is in Configuration mode (see Section 10.0 “Modes of Operation”). 5.5.1 CNF1 The BRP<5:0> bits control the baud rate prescaler. ...

Page 42

... MCP2515 REGISTER 5-1: CNF1 – CONFIGURATION 1 (ADDRESS: 2Ah) R/W-0 R/W-0 R/W-0 SJW1 SJW0 BRP5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-6 SJW: Synchronization Jump Width Length bits <1:0> Length = Length = Length = Length = bit 5-0 BRP: Baud Rate Prescaler bits < ...

Page 43

... PHSEG2: PS2 Length bits<2:0> (PHSEG2 + Minimum valid setting for PS2 © 2010 Microchip Technology Inc. U-0 U-0 R/W-0 — — PHSEG22 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Q MCP2515 R/W-0 R/W-0 PHSEG21 PHSEG20 bit Bit is unknown DS21801F-page 43 ...

Page 44

... MCP2515 NOTES: DS21801F-page 44 © 2010 Microchip Technology Inc. ...

Page 45

... If this is not desired, the error interrupt service routine should address this. The Current Error mode of the MCP2515 can be read by the MCU via the EFLG register (see Register 6-3). Additionally, there is an error state warning flag bit ...

Page 46

... MCP2515 FIGURE 6-1: ERROR MODES STATE DIAGRAM REC < 127 or TEC < 127 Error-Passive REGISTER 6-1: TEC – TRANSMIT ERROR COUNTER (ADDRESS: 1Ch) R-0 R-0 R-0 TEC7 TEC6 TEC5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 TEC: Transmit Error Count bits < ...

Page 47

... Set when TEC or REC is equal to or greater than 96 (TXWAR or RXWAR = 1) Reset when both REC and TEC are less than 96 - © 2010 Microchip Technology Inc. R-0 R-0 R-0 TXEP RXEP TXWAR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared MCP2515 R-0 R-0 RXWAR EWARN bit Bit is unknown DS21801F-page 47 ...

Page 48

... MCP2515 NOTES: DS21801F-page 48 © 2010 Microchip Technology Inc. ...

Page 49

... The CANINTF register contains the corresponding interrupt flag bit for each interrupt source. When an interrupt occurs, the INT pin is driven low by the MCP2515 and will remain low until the interrupt is cleared by the MCU. An interrupt can not be cleared if the respective condition still prevails ...

Page 50

... MCP2515 7.6.2 RECEIVER WARNING The REC has reached the MCU warning limit of 96. 7.6.3 TRANSMITTER WARNING The TEC has reached the MCU warning limit of 96. 7.6.4 RECEIVER ERROR-PASSIVE The REC has exceeded the error-passive limit of 127 and the device has gone to error-passive state. ...

Page 51

... RX0IF: Receive Buffer 0 Full Interrupt Flag bit 1 = Interrupt pending (must be cleared by MCU to reset interrupt condition interrupt pending © 2010 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 TX2IF TX1IF TX0IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared MCP2515 R/W-0 R/W-0 RX1IF RX0IF bit Bit is unknown DS21801F-page 51 ...

Page 52

... MCP2515 NOTES: DS21801F-page 52 © 2010 Microchip Technology Inc. ...

Page 53

... OSCILLATOR The MCP2515 is designed to be operated with a crystal or ceramic resonator connected to the OSC1 and OSC2 pins. The MCP2515 oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturer’s specifications. A typical oscillator circuit ...

Page 54

... MCP2515 FIGURE 8-3: EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT 330 kΩ 74AS04 0.1 mF Note 1: Duty cycle restrictions must be observed (see TABLE 8-1: CAPACITOR SELECTION FOR CERAMIC RESONATORS Typical Capacitor Values Used: Mode Freq. OSC1 HS 8.0 MHz 27 pF 16.0 MHz 22 pF Capacitor values are for design guidance only: These capacitors were tested with the resonators listed below for basic start-up and operation ...

Page 55

... RESET The MCP2515 differentiates between two resets: 1. Hardware Reset – Low on RESET pin 2. SPI Reset – Reset via SPI command Both of these resets are functionally equivalent important to provide one of these two resets after power-up to ensure that the logic and registers are in their default state ...

Page 56

... MCP2515 NOTES: DS21801F-page 56 © 2010 Microchip Technology Inc. ...

Page 57

... Filter registers • Mask registers 10.2 Sleep Mode The MCP2515 has an internal Sleep mode that is used to minimize the current consumption of the device. The SPI interface remains active for reading even when the MCP2515 is in Sleep mode, allowing access to all registers. ...

Page 58

... Normal Mode Normal mode is the standard operating mode of the MCP2515. In this mode, the device actively monitors all bus messages and generates acknowledge bits, error frames, etc. This is also the only mode in which the MCP2515 will transmit messages over the CAN bus. ...

Page 59

... TXB2 Interrupt 110 = RXB0 Interrupt 111 = RXB1 Interrupt bit 0 Unimplemented: Read as ‘0’ © 2010 Microchip Technology Inc. U-0 R-0 R-0 — ICOD2 ICOD1 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared MCP2515 R-0 U-0 ICOD0 — bit Bit is unknown DS21801F-page 59 ...

Page 60

... MCP2515 NOTES: DS21801F-page 60 © 2010 Microchip Technology Inc. ...

Page 61

... REGISTER MAP The register map for the MCP2515 is shown in Table 11-1. Address locations for each register are determined by using the column (higher-order 4 bits) and row (lower-order 4 bits) values. The registers have been arranged to optimize the sequential TABLE 11-1: CAN CONTROLLER REGISTER MAP ...

Page 62

... MCP2515 NOTES: DS21801F-page 62 © 2010 Microchip Technology Inc. ...

Page 63

... Mode 0,0 and Mode 1,1. Commands and data are sent to the device via the SI pin, with data being clocked in on the rising edge of SCK. Data is driven out by the MCP2515 (on the SO line) on the falling edge of SCK. The CS pin must be held low while any operation is performed. ...

Page 64

... DS21801F-page 64 The part is selected by lowering the CS pin and the Bit Modify command byte is then sent to the MCP2515. The command is followed by the address of the register, the mask byte and finally the data byte. The mask byte determines which bits in the register will be allowed to change. A ‘ ...

Page 65

... high-impedance MCP2515 don’t care data out Address Points to Address 0 0 Receive Buffer 0, 0x61 Start at RXB0SIDH 0 1 Receive Buffer 0, 0x66 Start at RXB0D0 1 0 Receive Buffer 1, 0x71 Start at RXB1SIDH 1 1 Receive Buffer 1, 0x76 Start at RXB1D0 ...

Page 66

... MCP2515 FIGURE 12-5: LOAD TX BUFFER SCK instruction high-impedance SO FIGURE 12-6: REQUEST-TO-SEND (RTS) INSTRUCTION SCK FIGURE 12-7: BIT MODIFY INSTRUCTION SCK instruction Note: Not all registers can be accessed with this command. See the register map for a list of the registers that apply. DS21801F-page 66 ...

Page 67

... Msg Type Received 0 0 Standard data frame 0 1 Standard remote frame 1 0 Extended data frame 1 1 Extended remote frame The extended ID bit is mapped to bit 4. The RTR bit is mapped to bit 3. MCP2515 23 repeat data out CANINTF.RX0IF CANINTFL.RX1IF TXB0CNTRL.TXREQ CANINTF.TX0IF TXB1CNTRL.TXREQ CANINTF.TX1IF TXB2CNTRL.TXREQ CANINTF.TX2IF ...

Page 68

... MCP2515 FIGURE 12-10: SPI INPUT TIMING CS 1 Mode 1,1 SCK Mode 0 MSB in SO FIGURE 12-11: SPI OUTPUT TIMING SCK 12 SO MSB out SI DS21801F-page high-impedance 13 don’t care LSB in 2 Mode 1,1 Mode 0,0 14 LSB out © 2010 Microchip Technology Inc. ...

Page 69

... Exposure to maximum rating conditions for extended periods may affect device reliability. © 2010 Microchip Technology Inc. MCP2515 +1.0V DD DS21801F-page 69 ...

Page 70

... MCP2515 TABLE 13-1: DC CHARACTERISTICS DC Characteristics Param. No. Sym Characteristic V Supply Voltage DD V Register Retention Voltage RET High-Level Input Voltage V RXCAN IH SCK, CS, SI, TXnRTS Pins OSC1 RESET Low-Level Input Voltage V RXCAN, TXnRTS Pins IL SCK, CS, SI OSC1 RESET Low-Level Output Voltage V TXCAN OL RXnBF Pins ...

Page 71

... AMB Min Max Units 100 — ns Industrial (I -40°C to +85°C AMB Extended (E -40°C to +125°C AMB Min Max Units 2 — µs MCP2515 V = 2. 4.5V to 5.5V DD Conditions + T ) OSH OSL V = 2. 4.5V to 5.5V DD Conditions V = 2. ...

Page 72

... MCP2515 TABLE 13-5: CLKOUT PIN AC CHARACTERISTICS CLKOUT Pin AC/DC Characteristics Param. Sym Characteristic No. t CLKOUT Pin High Time h CLKOUT t CLKOUT Pin Low Time l CLKOUT t CLKOUT Pin Rise Time r CLKOUT t CLKOUT Pin Fall Time f CLKOUT t CLOCKOUT Propagation Delay d CLKOUT 15 t Start-Of-Frame High Time ...

Page 73

... AMB Extended (E -40°C to +125°C AMB Min Max Units — 10 MHz 50 — — — — — ns — 2 µs Note 1 — 2 µs Note 1 45 — — — — ns — — ns — 100 ns MCP2515 V = 2. 4.5V to 5.5V DD Conditions DS21801F-page 73 ...

Page 74

... MCP2515 NOTES: DS21801F-page 74 © 2010 Microchip Technology Inc. ...

Page 75

... In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2010 Microchip Technology Inc. MCP2515 Example: e MCP2515-I/P^^ 3 0434256 Example: MCP2515 e E/SO^^ 3 1035256 Example: MCP2515 e IST ^ 256 3 1035 Example: 2515 e E/ML^^ 3 035256 DS21801F-page 75 ...

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... MCP2515 N NOTE DS21801F-page © 2010 Microchip Technology Inc. ...

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... D N NOTE © 2010 Microchip Technology Inc α φ A2 β MCP2515 c DS21801F-page 77 ...

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... MCP2515 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS21801F-page 78 © 2010 Microchip Technology Inc. ...

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... D N NOTE © 2010 Microchip Technology Inc MCP2515 φ L DS21801F-page 79 ...

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... MCP2515 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS21801F-page 80 © 2010 Microchip Technology Inc. ...

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... D TOP VIEW A3 © 2010 Microchip Technology Inc. EXPOSED PAD NOTE 1 BOTTOM VIEW A A1 MCP2515 DS21801F-page 81 ...

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... MCP2515 DS21801F-page 82 © 2010 Microchip Technology Inc. ...

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... Section 12.0 “SPI Interface”, Table - Changed supply voltage minimum to 2.7V. - Internal Capacitance: Changed 0V. - Standby Current (Sleep mode): Split specification into -40°C to +85°C and -40°C to +125°C. Revision A (May 2003) • Original Release of this Document. © 2010 Microchip Technology Inc. 12-1: condition MCP2515 DS21801F-page 83 ...

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... MCP2515 NOTES: DS21801F-page 84 © 2010 Microchip Technology Inc. ...

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... Extended Temperature, 18LD PDIP package. b) MCP2515-I/P: Industrial Temperature, 18LD PDIP package. c) MCP2515-E/SO: Extended Temperature, 18LD SOIC package. d) MCP2515-I/SO: Industrial Temperature, 18LD SOIC package. e) MCP2515T-I/SO: Tape and Reel, Industrial Temperature, 18LD SOIC package. f) MCP2515-I/ST: Industrial Temperature, 20LD TSSOP package. g) MCP2515T-I/ST: Tape and Reel, Industrial Temperature, 20LD TSSOP package ...

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... MCP2515 NOTES: DS21801F-page 86 © 2007 Microchip Technology Inc. ...

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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...

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... Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-213-7830 Fax: 886-7-330-9305 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2010 Microchip Technology Inc. 08/04/10 ...

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