MCP2515-E/PRB2 Microchip Technology, MCP2515-E/PRB2 Datasheet
MCP2515-E/PRB2
Related parts for MCP2515-E/PRB2
MCP2515-E/PRB2 Summary of contents
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... Controller Area Network (CAN) controller that imple- ments the CAN specification, version 2.0B capable of transmitting and receiving both standard and extended data and remote frames. The MCP2515 has two acceptance masks and six acceptance filters that are used to filter out unwanted messages, thereby reducing the host MCUs overhead ...
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... MCP2515 NOTES: DS21801E-page 2 © 2007 Microchip Technology Inc. ...
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... Microchip Technology Inc. 1.2 Control Logic The control logic block controls the setup and operation of the MCP2515 by interfacing to the other blocks in order to pass information and control. Interrupt pins are provided to allow greater system flexibility. There is one multi-purpose interrupt pin (as well as specific interrupt pins) for each of the receive ...
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... Chip select input pin for SPI interface I Active low device reset input P Positive supply for logic and I/O pins No internal connection Node Controller SPI MCP2515 TX RX XCVR Alternate Pin Function — — Start-of-Frame signal General purpose digital input. 100 kΩ internal pull- General purpose digital input ...
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... Transmit/Receive Buffers/Masks/ Filters The MCP2515 has three transmit and two receive buffers, two acceptance masks (one for each receive buffer) and a total of six acceptance filters. shows a block diagram of these buffers and their connection to the protocol engine. FIGURE 1-3: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM ...
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... MCP2515 1.5 CAN Protocol Engine The CAN protocol engine combines several functional blocks, shown in Figure 1-4 and described below. 1.5.1 PROTOCOL FINITE STATE MACHINE The heart of the engine is the Finite State Machine (FSM). The FSM is a sequencer that controls the sequential data stream between the TX/RX shift register, the CRC register and the bus line ...
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... CAN MESSAGE FRAMES The MCP2515 supports standard data frames, extended data frames and remote frames (standard and extended), as defined in the CAN 2.0B specification. 2.1 Standard Data Frame The CAN standard data frame is shown in As with all other frames, the frame begins with a Start- Of-Frame (SOF) bit, which is of the dominant state and allows hard synchronization of all nodes ...
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... Note: Case 2 should never occur with the MCP2515 due to very short internal delays. 2.6 Interframe Space The interframe space separates a preceding frame (of any type) from a subsequent data or remote frame. ...
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... FIGURE 2-1: STANDARD DATA FRAME © 2007 Microchip Technology Inc. Del ACK Bit Slot Ack Del CRC DLC0 DLC3 RB0 Bit Reserved IDE RTR ID0 ID3 10 ID Start-of-Frame MCP2515 DS21801E-page 9 ...
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... MCP2515 FIGURE 2-2: EXTENDED DATA FRAME DS21801E-page 10 Del ACK Bit Slot Ack Del CRC DLC0 DLC3 RB0 bits Reserved RB1 RTR EID0 EID17 IDE SRR ID0 ID3 ID10 Start-Of-Frame © 2007 Microchip Technology Inc. ...
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... FIGURE 2-3: REMOTE FRAME © 2007 Microchip Technology Inc. Del ACK Bit Slot Ack Del CRC DLC0 DLC3 RB0 bits Reserved RB1 RTR EID0 EID17 IDE SRR ID0 ID3 ID10 Start-Of-Frame MCP2515 DS21801E-page 11 ...
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... MCP2515 FIGURE 2-4: ACTIVE ERROR FRAME Start-Of-Frame DS21801E-page 12 DLC0 DLC3 RB0 Bit Reserved IDE RTR ID0 ID3 10 ID © 2007 Microchip Technology Inc. ...
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... FIGURE 2-5: OVERLOAD FRAME © 2007 Microchip Technology Inc. Del ACK Bit Slot Ack Del CRC DLC0 DLC3 RB0 IDE RTR ID0 10 ID Start-Of-Frame MCP2515 DS21801E-page 13 ...
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... MCP2515 NOTES: DS21801E-page 14 © 2007 Microchip Technology Inc. ...
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... Transmit Priority Transmit priority is a prioritization within the MCP2515 of the pending transmittable messages. This is independent from, and not necessarily related to, any prioritization implicit in the message arbitration scheme built into the CAN protocol. ...
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... Configuration and control of these pins is accomplished using the TXRTSCTRL register (see Register 3-3). The TXRTSCTRL register can only be modified when the MCP2515 is in Configuration mode (see Section 10.0 “Modes of Operation”). If configured to operate as a request-to-send pin, the pin is mapped into the respective TXBnCTRL.TXREQ bit for the transmit buffer ...
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... CTRL.ABAT bit before the message has started transmission, will abort the message TXBnCTRL.TXREQ=0 or CANCTRL.ABAT=1 ? Yes Yes Was Message error No or Lost arbitration ? Lost Arbitration Set TxB CTRL.MLOA N No Set MCP2515 No Message Error Set TxBnCTRL.TXERR Yes CANINTE.MEERE? No Generate Interrupt Set CANTINF.MERRF DS21801E-page 17 ...
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... MCP2515 REGISTER 3-1: TXBnCTRL – TRANSMIT BUFFER n CONTROL REGISTER (ADDRESS: 30h, 40h, 50h) U-0 R-0 R-0 — ABTF MLOA bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 Unimplemented: Read as ‘0’ bit 6 ABTF: Message Aborted Flag bit 1 = Message was aborted ...
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... Microchip Technology Inc. R-x R-x R/W-0 B1RTS B0RTS B2RTSM U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-x R/W-x R/W-x SID7 SID6 SID5 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared MCP2515 R/W-0 R/W-0 B1RTSM B0RTSM bit Bit is unknown R/W-x R/W-x SID4 SID3 bit Bit is unknown DS21801E-page 19 ...
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... MCP2515 REGISTER 3-4: TXBnSIDL – TRANSMIT BUFFER n STANDARD IDENTIFIER LOW (ADDRESS: 32h, 42h, 52h) R/W-x R/W-x R/W-x SID2 SID1 SID0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 SID: Standard Identifier bits <2:0> bit 4 Unimplemented: Reads as ‘0’ bit 3 EXIDE: Extended Identifier Enable bit ...
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... Microchip Technology Inc. R/W-x R/W-x R/W-x — DLC3 DLC2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-x R/W-x R/W-x TXBnDm4 TXBnDm3 TXBnDm2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared MCP2515 R/W-x R/W-x DLC1 DLC0 bit Bit is unknown R/W-x R/W-x TXBnDm1 TXBnDm0 bit Bit is unknown DS21801E-page 21 ...
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... MCP2515 NOTES: DS21801E-page 22 © 2007 Microchip Technology Inc. ...
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... MESSAGE RECEPTION 4.1 Receive Message Buffering The MCP2515 includes two full receive buffers with multiple acceptance filters for each. There is also a separate Message Assembly Buffer (MAB) that acts as a third receive buffer (see Figure 4-2). 4.1.1 MESSAGE ASSEMBLY BUFFER Of the three receive buffers, the MAB is always committed to receiving the next message from the bus ...
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... MCP2515 4.3 Start-of-Frame Signal If enabled, the Start-Of-Frame signal is generated on the SOF pin at the beginning of each CAN message detected on the RXCAN pin. The RXCAN pin monitors an idle bus for a recessive- to-dominant edge. If the dominant condition remains until the sample point, the DSTEMP interprets this as a SOF and a SOF pulse is generated ...
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... Acceptance Filter Acceptance Mask Acceptance Filter RXM0 Acceptance Filter Acceptance Filter RXF0 Acceptance Filter Acceptance Filter RXF1 M Identifier A B Data Field MCP2515 CONFIGURING RXNBF PINS Pin Status Disabled, high-impedance X Receive buffer interrupt X Digital output = 0 0 Digital output = 1 1 RXM1 RXF2 RXF3 A ...
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... MCP2515 FIGURE 4-3: RECEIVE FLOW FLOWCHART Determines if the receive register is empty and able to accept a new message CANINTF.RX0IF = ? Yes Generate Overflow Error: Move message into RXB0 1 Set CANINTF.RX0IF = Set RXB0CTRL.FILHIT <0> according to which filter criteria Yes 1 CANINTE.RX0IE = ? No Are 1 BFPCTRL.B0BFM = Yes and 1 BF1CTRL.B0BFE = ? No DS21801E-page 26 ...
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... BUKT: Rollover Enable bit 1 = RXB0 message will rollover and be written to RXB1 if RXB0 is full 0 = Rollover disabled bit 1 BUKT1: Read-only Copy of BUKT bit (used internally by the MCP2515) bit 0 FILHIT: Filter Hit bit - indicates which acceptance filter enabled reception of message 1 = Acceptance Filter 1 (RXF1 Acceptance Filter 0 (RXF0) ...
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... MCP2515 REGISTER 4-2: RXB1CTRL – RECEIVE BUFFER 1 CONTROL (ADDRESS: 70h) U-0 R/W-0 R/W-0 — RXM1 RXM0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 Unimplemented: Read as ‘0’ bit 6-5 RXM: Receive Buffer Operating Mode bits 11 = Turn mask/filters off; receive any message ...
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... Microchip Technology Inc. R/W-0 R/W-0 R/W-0 B0BFS B1BFE B0BFE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R-x R-x R-x SID7 SID6 SID5 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared MCP2515 R/W-0 R/W-0 B1BFM B0BFM bit Bit is unknown R-x R-x SID4 SID3 bit Bit is unknown DS21801E-page 29 ...
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... MCP2515 REGISTER 4-5: RXBnSIDL – RECEIVE BUFFER n STANDARD IDENTIFIER LOW (ADDRESS: 62h, 72h) R-x R-x R-x SID2 SID1 SID0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 SID: Standard Identifier bits <2:0> These bits contain the three least significant bits of the Standard Identifier for the received message bit 4 SRR: Standard Frame Remote Transmit Request bit (valid only if IDE bit = ‘ ...
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... Bit is cleared R-x R-x R-x EID4 EID3 EID2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R-x R-x R-x RBnDm4 RBnDm3 RBnDm2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared MCP2515 R-x R-x EID1 EID0 bit Bit is unknown R-x R-x EID1 EID0 bit Bit is unknown R-x R-x RBnDm1 RBnDm0 ...
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... MCP2515 4.5 Message Acceptance Filters and Masks The message acceptance filters and masks are used to determine if a message in the message assembly buffer should be loaded into either of the receive buffers (see Figure 4-5). Once a valid message has been received into the MAB, the identifier fields of the message are compared to the filter values ...
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... This implies that RXB0 has a higher priority than RXB1. 4.5.5 CONFIGURING THE MASKS AND FILTERS The mask and filter registers can only be modified when the MCP2515 is in Configuration mode (see Section 10.0 “Modes of Operation”). Acceptance Mask Register RXMn 0 RXMn ...
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... MCP2515 REGISTER 4-10: RXFnSIDH – FILTER n STANDARD IDENTIFIER HIGH (ADDRESS: 00h, 04h, 08h, 10h, 14h, 18h) R/W-x R/W-x R/W-x SID10 SID9 SID8 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 SID: Standard Identifier Filter bits <10:3> These bits hold the filter bits to be applied to bits <10:3> of the Standard Identifier portion of a received ...
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... Bit is cleared R/W-x R/W-x R/W-x EID4 EID3 EID2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 R/W-0 SID7 SID6 SID5 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared MCP2515 R/W-x R/W-x EID9 EID8 bit Bit is unknown R/W-x R/W-x EID1 EID0 bit Bit is unknown R/W-0 R/W-0 SID4 SID3 ...
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... MCP2515 REGISTER 4-15: RXMnSIDL – MASK n STANDARD IDENTIFIER LOW (ADDRESS: 21h, 25h) R/W-0 R/W-0 R/W-0 SID2 SID1 SID0 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-5 SID: Standard Identifier Mask bits <2:0> These bits hold the mask bits to be applied to bits<2:0> of the Standard Identifier portion of a received ...
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... Digital Phase Lock Loop (DPLL) synchronization. The bit timing of the MCP2515 is implemented using a DPLL that is configured to synchronize to the incoming data, as well as provide the nominal timing for the transmitted data ...
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... MCP2515 PROPAGATION SEGMENT The Propagation Segment (PropSeg) exists to compensate for physical delays between nodes. The propagation delay is defined as twice the sum of the signal’s propagation time on the bus line, including the delays associated with the bus driver. The PropSeg is programmable from 1 – 8 TQ. ...
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... A transmitting node will not resynchronize on a positive phase error (e > 0 the absolute magnitude of the phase error is greater than the SJW, the appropriate phase segment will adjust by an amount equal to the SJW. MCP2515 DS21801E-page 39 ...
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... MCP2515 FIGURE 5-3: SYNCHRONIZING THE BIT TIME Input Signal ( PropSeg SyncSeg SJW (PS1) Input Signal (e > 0) PropSeg SyncSeg SJW (PS1) Resynchronization to a Slower Transmitter (e > 0) Input Signal (e < 0) SyncSeg PropSeg SJW (PS1) Resynchronization to a Faster Transmitter (e < 0) DS21801E-page 40 PhaseSeg1 (PS1) Sample ...
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... Bit Timing Configuration Registers The configuration registers (CNF1, CNF2, CNF3) control the bit timing for the CAN bus interface. These registers can only be modified when the MCP2515 is in Configuration mode (see Section 10.0 “Modes of Operation”). 5.5.1 CNF1 The BRP<5:0> bits control the baud rate prescaler. ...
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... MCP2515 REGISTER 5-1: CNF1 – CONFIGURATION 1 (ADDRESS: 2Ah) R/W-0 R/W-0 R/W-0 SJW1 SJW0 BRP5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-6 SJW: Synchronization Jump Width Length bits <1:0> Length = Length = Length = Length = bit 5-0 BRP: Baud Rate Prescaler bits < ...
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... Unimplemented: Reads as ‘0’ bit 2-0 PHSEG2: PS2 Length bits<2:0> (PHSEG2 + Minimum valid setting for PS2 © 2007 Microchip Technology Inc. U-0 U-0 R/W-0 — — PHSEG22 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Q MCP2515 R/W-0 R/W-0 PHSEG21 PHSEG20 bit Bit is unknown DS21801E-page 43 ...
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... MCP2515 NOTES: DS21801E-page 44 © 2007 Microchip Technology Inc. ...
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... If this is not desired, the error interrupt service routine should address this. The Current Error mode of the MCP2515 can be read by the MCU via the EFLG register (see Register 6-3). Additionally, there is an error state warning flag bit ...
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... MCP2515 FIGURE 6-1: ERROR MODES STATE DIAGRAM REC < 127 or TEC < 127 Error-Passive REGISTER 6-1: TEC – TRANSMIT ERROR COUNTER (ADDRESS: 1Ch) R-0 R-0 R-0 TEC7 TEC6 TEC5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 TEC: Transmit Error Count bits <7:0> REGISTER 6-2: REC – ...
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... Set when TEC or REC is equal to or greater than 96 (TXWAR or RXWAR = 1) Reset when both REC and TEC are less than 96 - © 2007 Microchip Technology Inc. R-0 R-0 R-0 TXEP RXEP TXWAR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared MCP2515 R-0 R-0 RXWAR EWARN bit Bit is unknown DS21801E-page 47 ...
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... MCP2515 NOTES: DS21801E-page 48 © 2007 Microchip Technology Inc. ...
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... The CANINTF register contains the corresponding interrupt flag bit for each interrupt source. When an interrupt occurs, the INT pin is driven low by the MCP2515 and will remain low until the interrupt is cleared by the MCU. An interrupt can not be cleared if the respective condition still prevails ...
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... MCP2515 7.6.2 RECEIVER WARNING The REC has reached the MCU warning limit of 96. 7.6.3 TRANSMITTER WARNING The TEC has reached the MCU warning limit of 96. 7.6.4 RECEIVER ERROR-PASSIVE The REC has exceeded the error-passive limit of 127 and the device has gone to error-passive state. 7.6.5 TRANSMITTER ERROR-PASSIVE The TEC has exceeded the error- passive limit of 127 and the device has gone to error- passive state ...
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... RX0IF: Receive Buffer 0 Full Interrupt Flag bit 1 = Interrupt pending (must be cleared by MCU to reset interrupt condition interrupt pending © 2007 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 TX2IF TX1IF TX0IF U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared MCP2515 R/W-0 R/W-0 RX1IF RX0IF bit Bit is unknown DS21801E-page 51 ...
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... MCP2515 NOTES: DS21801E-page 52 © 2007 Microchip Technology Inc. ...
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... OSCILLATOR The MCP2515 is designed to be operated with a crystal or ceramic resonator connected to the OSC1 and OSC2 pins. The MCP2515 oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. A typical oscillator circuit ...
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... MCP2515 FIGURE 8-3: EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT 330 kΩ 74AS04 0.1 mF Note 1: Duty cycle restrictions must be observed (see TABLE 8-1: CAPACITOR SELECTION FOR CERAMIC RESONATORS Typical Capacitor Values Used: Mode Freq. OSC1 HS 8.0 MHz 27 pF 16.0 MHz 22 pF Capacitor values are for design guidance only: These capacitors were tested with the resonators listed below for basic start-up and operation ...
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... RESET The MCP2515 differentiates between two resets: 1. Hardware Reset – Low on RESET pin. 2. SPI Reset – Reset via SPI command. Both of these resets are functionally equivalent important to provide one of these two resets after power-up to ensure that the logic and registers are in their default state ...
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... MCP2515 NOTES: DS21801E-page 56 © 2007 Microchip Technology Inc. ...
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... TXRTSCTRL • Filter registers • Mask registers 10.2 Sleep Mode The MCP2515 has an internal Sleep mode that is used to minimize the current consumption of the device. The SPI interface remains active for reading even when the MCP2515 is in Sleep mode, allowing access to all registers. ...
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... Normal Mode Normal mode is the standard operating mode of the MCP2515. In this mode, the device actively monitors all bus messages and generates acknowledge bits, error frames, etc. This is also the only mode in which the MCP2515 will transmit messages over the CAN bus. ...
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... TXB1 Interrupt 101 = TXB2 Interrupt 110 = RXB0 Interrupt 111 = RXB1 Interrupt bit 0 Unimplemented: Read as ‘0’ © 2007 Microchip Technology Inc. U-0 R-0 R-0 — ICOD2 ICOD1 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared MCP2515 R-0 U-0 ICOD0 — bit Bit is unknown DS21801E-page 59 ...
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... MCP2515 NOTES: DS21801E-page 60 © 2007 Microchip Technology Inc. ...
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... REGISTER MAP The register map for the MCP2515 is shown in Table 11-1. Address locations for each register are determined by using the column (higher-order 4 bits) and row (lower-order 4 bits) values. The registers have been arranged to optimize the sequential TABLE 11-1: CAN CONTROLLER REGISTER MAP Lower ...
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... MCP2515 NOTES: DS21801E-page 62 © 2007 Microchip Technology Inc. ...
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... Mode 0,0 and Mode 1,1. Commands and data are sent to the device via the SI pin, with data being clocked in on the rising edge of SCK. Data is driven out by the MCP2515 (on the SO line) on the falling edge of SCK. The CS pin must be held low while any operation is performed. ...
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... DS21801E-page 64 The part is selected by lowering the CS pin and the Bit Modify command byte is then sent to the MCP2515. The command is followed by the address of the register, the mask byte and finally the data byte. The mask byte determines which bits in the register will be allowed to change. A ‘ ...
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... high-impedance MCP2515 23 don’t care data out Address Points to Address 0 0 Receive Buffer 0, 0x61 Start at RXB0SIDH 0 1 Receive Buffer 0, ...
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... MCP2515 FIGURE 12-5: LOAD TX BUFFER SCK instruction high-impedance SO FIGURE 12-6: REQUEST-TO-SEND (RTS) INSTRUCTION SCK FIGURE 12-7: BIT MODIFY INSTRUCTION SCK ...
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... Msg Type Received 0 0 Standard data frame 0 1 Standard remote frame 1 0 Extended data frame 1 1 Extended remote frame The extended ID bit is mapped to bit 4. The RTR bit is mapped to bit 3. MCP2515 23 repeat data out CANINTF.RX0IF CANINTFL.RX1IF TXB0CNTRL ...
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... MCP2515 FIGURE 12-10: SPI INPUT TIMING CS 1 Mode 1,1 SCK Mode 0 MSB in SO FIGURE 12-11: SPI OUTPUT TIMING SCK 12 SO MSB out SI DS21801E-page high-impedance 13 don’t care LSB in 2 Mode 1,1 Mode 0,0 14 LSB out © 2007 Microchip Technology Inc. ...
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... Exposure to maximum rating conditions for extended periods may affect device reliability. © 2007 Microchip Technology Inc. MCP2515 +1.0V DD DS21801E-page 69 ...
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... MCP2515 TABLE 13-1: DC CHARACTERISTICS DC Characteristics Param. No. Sym Characteristic V Supply Voltage DD V Register Retention Voltage RET High-Level Input Voltage V RXCAN IH SCK, CS, SI, TXnRTS Pins OSC1 RESET Low-Level Input Voltage V RXCAN, TXnRTS Pins IL SCK, CS, SI OSC1 RESET Low-Level Output Voltage V TXCAN OL RXnBF Pins SO, CLKOUT ...
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... Extended (E -40°C to +125°C AMB Min Max Units 100 — ns Industrial (I -40°C to +85°C AMB Extended (E -40°C to +125°C AMB Min Max Units 2 — µs MCP2515 V = 2. 4.5V to 5.5V DD Conditions + T ) OSH OSL V = 2. 4.5V to 5.5V DD Conditions V = 2. 4.5V to 5.5V ...
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... MCP2515 TABLE 13-5: CLKOUT PIN AC CHARACTERISTICS CLKOUT Pin AC/DC Characteristics Param. Sym Characteristic No. t CLKOUT Pin High Time h CLKOUT t CLKOUT Pin Low Time l CLKOUT t CLKOUT Pin Rise Time r CLKOUT t CLKOUT Pin Fall Time f CLKOUT t CLOCKOUT Propagation Delay d CLKOUT 15 t Start-Of-Frame High Time ...
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... AMB Min Max Units — 10 MHz 50 — — — — — ns — 2 µs Note 1 — 2 µs Note 1 45 — — — — ns — — ns — 100 ns MCP2515 V = 2. 4.5V to 5.5V DD Conditions DS21801E-page 73 ...
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... MCP2515 NOTES: DS21801E-page 74 © 2007 Microchip Technology Inc. ...
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... In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2007 Microchip Technology Inc. MCP2515 Example: e MCP2515-I/P^^ 3 0434256 Example: MCP2515 e E/SO^^ 3 0434256 Example: MCP2515 e IST ^ 256 3 0434 DS21801E-page 75 ...
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... MCP2515 N NOTE DS21801E-page © 2007 Microchip Technology Inc. ...
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... D N NOTE © 2007 Microchip Technology Inc α φ A2 β MCP2515 c DS21801E-page 77 ...
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... MCP2515 D N NOTE DS21801E-page © 2007 Microchip Technology Inc. φ L ...
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... Section 12.0 “SPI Interface”, Table 12-1: - Changed supply voltage minimum to 2.7V. - Internal Capacitance: Changed 0V. - Standby Current (Sleep mode): Split specification into -40°C to +85°C and -40°C to +125°C. Revision A (May 2003) • Original Relase of this Document. © 2007 Microchip Technology Inc. condition MCP2515 DS21801E-page 79 ...
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... MCP2515 NOTES: DS21801E-page 80 © 2007 Microchip Technology Inc. ...
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... To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office PART NO. – X /XX Device Temperature Package Range Device MCP2515: CAN Controller w/ SPI Interface MCP2515T: CAN Controller w/SPI Interface (Tape and Reel) Temperature I = -40°C to +85°C (Industrial) Range E = -40°C to +125°C (Extended) Package P = Plastic DIP (300 mil Body), 18-Lead ...
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... MCP2515 NOTES: DS21801E-page 82 © 2007 Microchip Technology Inc. ...
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... PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 © 2007 Microchip Technology Inc. EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris ...