IDT821054PQF IDT, Integrated Device Technology Inc, IDT821054PQF Datasheet - Page 30

• Manufacturer Part Number: IDT821054PQF
• Description: IC PCM CODEC QUAD MPI 64-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PCM Codec/Filterr

Specifications of IDT821054PQF

• Data Interface: PCM Audio Interface
• Number Of Adcs / Dacs: 4 / 4
• Sigma Delta: No
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-MQFP, 64-PQFP
• Single Supply Voltage (typ): 5V
• Single Supply Voltage (min): 4.75V
• Single Supply Voltage (max): 5.25V
• Package Type: PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 821054PQF

IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
GREG22: Global Loopback Control and PLL Power Down, Read/Write (35H/B5H)
GREG23: Over-sampling Timing Tuning, Read/Write (37H/B7H)
The Linear/Compressed bit (L/C) determines the mode of level meter operation.
L/C = 0:
L/C = 1:
GREG18 and GREG19.
The Level Meter Channel Select bits (CS[1:0]) select a channel, data on which will be level metered.
CS[1:0] = 00:
CS[1:0] = 01:
CS[1:0] = 10:
CS[1:0] = 11:
The PLL Power Down bit (PPD) controls the operation state of the PLL block.
PPD = 0:
PPD = 1:
The Loop Control bits determine the loopback status. Refer to
DLB_ANA = 0:
DLB_ANA = 1:
ALB_8k = 0:
ALB_8k = 1:
DLB_8k = 0:
DLB_8k = 1:
DLB_DI = 0:
DLB_DI = 1:
ALB_DI = 0:
ALB_DI = 1:
To improve the performance of total distortion, it is recommended to write a data byte of 40H to this register. The default value is 00H.
Command
Command
I/O data
R/W
R/W
b7
b7
Reserved
Message mode is selected. The compressed PCM data will be output to GREG19 transparently (default).
Metering mode is selected. The linear PCM data will be metered and the result will be output to the registers
Channel 1 is selected (default);
Channel 2 is selected;
Channel 3 is selected;
Channel 4 is selected.
The PLL is disabled. The device is in normal operation state (default);
The PLL is powered down. The device works in power-saving mode. All clocks stop running.
The Digital Loopback via Analog Interface is disabled (default);
The Digital Loopback via Analog Interface is enabled.
The Analog Loopback via 8 kHz Interface is disabled (default);
The Analog Loopback via 8 kHz Interface is enabled.
The Digital Loopback via 8 kHz Interface is disabled (default);
The Digital Loopback via 8 kHz Interface is enabled.
The Digital Loopback from DR to DX is disabled (default);
The Digital Loopback from DR to DX is enabled.
The Analog Loopback from DX to DR is disabled (default);
The Analog Loopback from DX to DR is enabled.
b6
b6
0
0
PPD
b5
b5
1
1
DLB_ANA
30
b4
b4
1
1
Figure - 4 on page 11
ALB_8k
b3
b3
0
0
for detailed information.
DLB_8k
b2
b2
1
1
INDUSTRIAL TEMPERATURE RANGE
DLB_DI
b1
b1
0
1
ALB_DI
b0
b0
1
1