IDT821054PQF IDT, Integrated Device Technology Inc, IDT821054PQF Datasheet - Page 28

• Manufacturer Part Number: IDT821054PQF
• Description: IC PCM CODEC QUAD MPI 64-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PCM Codec/Filterr

Specifications of IDT821054PQF

• Data Interface: PCM Audio Interface
• Number Of Adcs / Dacs: 4 / 4
• Sigma Delta: No
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-MQFP, 64-PQFP
• Single Supply Voltage (typ): 5V
• Single Supply Voltage (min): 4.75V
• Single Supply Voltage (max): 5.25V
• Package Type: PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 821054PQF

IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
GREG13: FSK Flag Length, Read/Write (2CH/ACH)
GREG14: FSK Data Length, Read/Write (2DH/ADH)
GREG15: FSK Seizure Length, Read/Write (2EH/AEH)
GREG16: FSK Mark Length, Read/Write (2FH/AFH)
GREG17: FSK Start, Mark After Send, BT/Bellcore Selection, FSK Channel Selection and FSK On/Off, Read/Write (30H/B0H)
pins respectively. When the SB3 pins of Channel 1 to Channel 4 are configured as outputs, the control data is written to these four SB3
pins via the SB3[0] to SB3[3] bits respectively.
The flag signal is a stream of ‘1’ which is transmitted between two message bytes during Caller-ID messages transmission. The Flag
Length bits FL[7:0] determine the number of the flag bits. The flag length can be from 0 to 255 (d) bits. The default flag length is 0 (i.e.
FL[7:0] = 00H), which means that no flag signal will be transmitted.
The Data Length bits DL[7:0] determine the number of the data bytes that will be transmitted except the flag signal. The data length can
be from 0 to 64 (d) bytes. Any value larger than 64 (d) in this register will be taken as 64 (d) by the CODEC. The default data length is 0
(d), which means that no data bytes will be transmitted.
The Seizure Length is the number of ‘01’ pairs that represent the seizure phase. The Seizure Length is two times of the value of the
SL[7:0] bits. The value of the SL[7:0] bits can be from 0 to 255 (d), corresponding to Seizure Length of 0 to 510 (d). The default value is
0 (d), which means that no seizure signal will be transmitted.
The Mark Length bits ML[7:0] determine the number of the mark bits of ‘1’, which is transmitted in initial flag phase. The Mark Length can
be from 0 to 255 (d). The default value is 0 (d), which means that no mark signal will be transmitted.
The FSK Channel Select bits (FCS[1:0]) select a channel on which the FSK signal is generated.
FCS[1:0] = 00:
FCS[1:0] = 01:
FCS[1:0] = 10:
FCS[1:0] = 11:
The FSK On/Off bit (FO) enables or disables the FSK function block.
FO = 0:
Command
Command
Command
Command
Command
I/O data
I/O data
I/O data
I/O data
I/O data
ML[7]
FL[7]
DL[7]
SL[7]
R/W
R/W
R/W
R/W
R/W
b7
b7
b7
b7
b7
Reserved
Channel 1 is selected (default);
Channel 2 is selected;
Channel 3 is selected;
Channel 4 is selected.
The FSK function block is disabled (default);
DL[6]
ML[6]
FL[6]
SL[6]
b6
b6
b6
b6
b6
0
0
0
0
0
FCS[1]
DL[5]
ML[5]
FL[5]
SL[5]
b5
b5
b5
b5
b5
1
1
1
1
1
FCS[0]
ML[4]
DL[4]
SL[4]
FL[4]
28
b4
b4
b4
b4
b4
0
0
0
0
1
ML[3]
FL[3]
DL[3]
SL[3]
FO
b3
b3
b3
b3
b3
1
1
1
1
0
ML[2]
FL[2]
DL[2]
SL[2]
BS
b2
b2
b2
b2
b2
1
1
1
1
0
INDUSTRIAL TEMPERATURE RANGE
DL[1]
ML[1]
FL[1]
SL[1]
MAS
b1
b1
b1
b1
b1
0
0
1
1
0
ML[0]
DL[0]
SL[0]
FL[0]
FS
b0
b0
b0
b0
b0
0
1
0
1
0