IDT821054PQF IDT, Integrated Device Technology Inc, IDT821054PQF Datasheet - Page 29

• Manufacturer Part Number: IDT821054PQF
• Description: IC PCM CODEC QUAD MPI 64-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PCM Codec/Filterr

Specifications of IDT821054PQF

• Data Interface: PCM Audio Interface
• Number Of Adcs / Dacs: 4 / 4
• Sigma Delta: No
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 4.75 V ~ 5.25 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-MQFP, 64-PQFP
• Single Supply Voltage (typ): 5V
• Single Supply Voltage (min): 4.75V
• Single Supply Voltage (max): 5.25V
• Package Type: PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 821054PQF

IDT821054 QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
GREG18: Level Meter Result Low Byte, Read Only (31H)
GREG19: Level Meter Result High Byte, Read Only (32H)
GREG20: Level Meter Count Number, Read/Write (33H/B3H)
GREG21: Level Meter Channel and Linear/Compressed Mode Selection, Level Meter On/Off, Read/Write (34H/B4H)
FO = 1:
The BT/Bellcore Select bit (BS) determines which specification the IDT821054 will follow:
BS = 0:
BS = 1:
The Mark After Send bit (MAS) determines if the FSK generator will keep on sending a mark-after-send signal (a stream of ‘1’) after
sending out all data in the FSK-RAM.
MAS = 0:
MAS = 1:
If the MAS bit is set to ‘0’ and the FS bit is set to ‘1’, the mark-after-send signal will be stopped.
The FSK Start bit (FS) should be set to ‘1’ to start sending FSK signal. It will be automatically reset after all data in the FSK-RAM has
been sent out. If the Seizure Length, Mark Length and Data Length are set to 0, the FS bit will be reset to ‘0’ immediately after it is set to
‘1’.
FS = 0:
FS = 1:
This register contains the low byte of the level meter result. The default value is 00H.
The LVLL[0] bit in this register will be set to ‘1’ when the level meter result (both high and low bytes) is ready, and it will be reset to ‘0’
immediately after the high byte of result is read. To read the level meter result, it is recommended to the low byte first, then read the high
byte (LVLH[7:0] in GREG19).
This register contains the high byte of the level meter result. The default value is 00H.
The CN[7:0] bits are used to set the number of time cycles for sampling the PCM data.
CN[7:0] = 0 (d):
CN[7:0] = N (d):
The Level Meter On/Off bit (LMO) enables/disables the level meter.
LMO = 0:
LMO = 1:
Command
Command
Command
Command
I/O data
I/O data
I/O data
I/O data
LVLH[7]
LVLL[7]
CN[7]
R/W
R/W
b7
b7
b7
b7
0
0
The output will be muted after all data in the FSK-RAM has been sent out (default);
The FSK function block is enabled.
Bellcore specification is selected (default);
BT specification is selected.
The FSK generator keeps on sending out a mark-after-send signal after sending out all data in the FSK-RAM.
FSK transmission is disabled (default);
FSK transmission starts.
the PCM data is output to the result registers GREG18 and GREG19 directly;
the PCM data is sampled for N × 125
The level meter is disabled (default);
The level meter is enabled.
LVLH[6]
LVLL[6]
CN[6]
b6
b6
b6
b6
0
0
0
0
Reserved
LVLH[5]
LVLL[5]
CN[5]
b5
b5
b5
b5
1
1
1
1
LVLH[4]
LVLL[4]
CN[4]
29
b4
b4
b4
b4
1
1
1
1
µ
s (N is from 1 to 255).
LVLH[3]
LVLL[3]
CN[3]
LMO
b3
b3
b3
b3
0
0
0
0
LVLH[2]
LVLL[2]
CN[2]
L/C
b2
b2
b2
b2
0
0
0
1
INDUSTRIAL TEMPERATURE RANGE
LVLH[1]
LVLL[1]
CN[1]
CS[1]
b1
b1
b1
b1
0
1
1
0
LVLH[0]
LVLL[0]
CN[0]
CS[0]
b0
b0
b0
b0
1
0
1
0