IDTSTAC9751XXTAEC1XR IDT, Integrated Device Technology Inc, IDTSTAC9751XXTAEC1XR Datasheet - Page 56

• Manufacturer Part Number: IDTSTAC9751XXTAEC1XR
• Description: IC CODEC AC'97 2CH VALUE 48-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9751XXTAEC1XR

• Resolution (bits): 18 b, 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 85 / 89
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9751XXTAEC1XR

7. LOW POWER MODES
IDT™
VALUE-LINE TWO-CHANNEL AC’97 CODECS
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS
The STAC9750/9751 is capable of operating at reduced power when no activity is required. The
state of power-down is controlled by the Powerdown Register (26h). There are 7 commands of sep-
arate power down. The power down options are listed in Table 40. The first three bits, PR0..PR2, can
be used individually or in combination with each other, and control power distribution to the ADCs,
DACs and Mixer. The last analog power control bit, PR3, affects analog bias and reference voltages,
and can only be used in combination with PR0, PR1, and PR2. PR3 essentially removes power from
all analog sections of the CODEC, and is generally only asserted when the CODEC will not be
needed for long periods. PR0 and PR1 control the PCM ADCs and DACs only. PR2 and PR3 do not
need to be “set” before a PR4, but PR0 and PR1 must be “set” before PR4. PR5 disables the internal
CODEC clock and requires an external cold reset for recovery. PR6 disables the headphone driver
amplifier for additional analog power saving.
The Figure 19 illustrates one example procedure to do a complete power down of STAC9750/9751.
From normal operation, sequential writes to the Powerdown Register are performed to power down
STAC9750/9751 a piece at a time. After everything has been shut off, a final write (of PR4) can be
executed to shut down the AC-Link. The part will remain in sleep mode with all its registers holding
their static values. To wake up, the AC'97 controller will send an extended pulse on the sync line,
issuing a warm reset. This will restart the AC-Link (resetting PR4 to zero). The STAC9750/9751 can
also be woken up with a cold reset. A cold reset will reset all of the registers to their default states.
When a section is powered back on, the Powerdown Control/Status register (index 26h) should be
read to verify that the section is ready (stable) before attempting any operation that requires it.
Normal
Figure 19. Example of STAC9750/9751 Powerdown/Powerup Flow
PR0=0 & ADC=1
PR0=1
GRP Bits
PR0
PR1
PR2
PR3
PR4
PR5
PR6
Ready =1
ADCs off PR0
PR1=0 & DAC=1
PR1=1
PCM in ADCs & Input Mux Powerdown
PCM out DACs Powerdown
Analog Mixer power down (VREF still on)
Analog Mixer power down (VREF off)
Digital Interface (AC-Link) power down (external clock off)
Internal Clock disable
Powerdown HEADPHONE_OUT
DACs off PR1
Table 40. Low Power Modes
Default
56
PR2=0 & ANL=1
PR2=1
PR2 or PR3
Analog off
Cold Reset
Function
PR4=1
STAC9750/9751
Digital I/F off
Warm Reset
PR4
Shut off
AC-Link
PC AUDIO
V 5.8 103106