IDTSTAC9751XXTAEC1XR IDT, Integrated Device Technology Inc, IDTSTAC9751XXTAEC1XR Datasheet - Page 41

• Manufacturer Part Number: IDTSTAC9751XXTAEC1XR
• Description: IC CODEC AC'97 2CH VALUE 48-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9751XXTAEC1XR

• Resolution (bits): 18 b, 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 85 / 89
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9751XXTAEC1XR

IDT™
VALUE-LINE TWO-CHANNEL AC’97 CODECS
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS
6.5.9.
6.5.10.
Bit(s)
13-12
10:0
15
14
11
EAPD
D15
D15
D7
D7
I4
Audio Interrupt (24h)
Default: 0000h
Powerdown Ctrl/Stat (26h)
Default: 000Fh
Reset
Value
0
0
0
0
0
R/W
RW
RW Reserved Bits not used, should read back 0
RW
RO
RO Reserved Bits not used, should read back 0
PR6
D14
D14
D6
D6
I3
Name
Reserved
I4
I3
I0
0 = Interrupt is clear
1 = Interrupt is set
Interrupt event is cleared by writing a 1 to this bit.
The interrupt bit will change regardless of condition of interrupt enable (I0) status.
An interrupt in the GPI in slot 12 in the AC-Link will follow this bit change when
interrupt enable (I0) is unmasked.
Interrupt Cause
0 = No Interrupt Caused
1 = Change in GPIO input status
These bits will reflect the general cause of the first interrupt event generated. It
should be read after interrupt status has been confirmed as interrupting. The
information should be used to scan possible interrupting events in proper pages.
Interrupt Enable
0 = Interrupt generation is masked.
1 = Interrupt generation is un-masked.
The driver should not un-mask the interrupt unless ensured by the AC ‘97 controller
that no conflict is possible with modem slot 12 - GPI functionality. Some AC’97 2.2
compliant controllers do not support audio CODEC interrupt infrastructure. In either
case, S/W should poll the interrupt status after initiating a sense cycle and wait for
Sense Cycle Max Delay to determine if an interrupting event has occurred.
PR5
D13
D13
D5
D5
Reserved
PR4
D12
D12
41
D4
D4
Reserved
PR3
REF
D11
D11
D3
D3
I0
Description
STAC9750/9751
PR2
ANL
D10
D10
D2
D2
Reserved
DAC
PR1
D9
D1
D9
D1
PC AUDIO
V 5.8 103106
ADC
PR0
D8
D0
D8
D0