IDTSTAC9750XXTAEC1XR IDT, Integrated Device Technology Inc, IDTSTAC9750XXTAEC1XR Datasheet - Page 29

• Manufacturer Part Number: IDTSTAC9750XXTAEC1XR
• Description: IC CODEC AC'97 2CH VALUE 48-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9750XXTAEC1XR

• Resolution (bits): 18 b, 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 85 / 89
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9750XXTAEC1XR

IDT™
VALUE-LINE TWO-CHANNEL AC’97 CODECS
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS
5.2.
AC-Link Low Power Mode
STAC9750/9751 ADCs are implemented to support 18-bit resolution.
STAC9750/9751 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0
to fill out its 20-bit time slot.
See section 6.5.25; page 51 for slot configurations and register settings.
5.1.2.11.
Audio input frame slot 11 is the right channel output of STAC9750/9751 input MUX, post-ADC.
STAC9750/9751 ADCs are implemented to support 18-bit resolution.
STAC9750/9751 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0
to fill out its 20-bit time slot.
See section 6.5.25; page 51 for slot configurations and register settings.
5.1.2.12. Slot 12: Reserved
Audio input frame slot 12 is Reserved for modem operation and is not used by the STAC9750/9751.
This slot is always stuffed with 0.
The STAC9750/9751 AC-Link can be placed in the low power mode by programming register 26h to
the appropriate value. Both BIT_CLK and SDATA_IN will be brought to, and held at a logic low volt-
age level. The AC'97 controller can wake up the STAC9750/9751 by providing the appropriate reset
signals.
BIT_CLK and SDATA_IN are transitioned low immediately (within the maximum specified time) fol-
lowing the decode of the write to the Powerdown Register (26h) with PR4. When the AC'97 control-
ler driver is at the point where it is ready to program the AC-Link into its low power mode, slots (1
and 2) are assumed to be the only valid stream in the audio output frame (all sources of audio input
have been neutralized).
SDATA_OUT
SDATA_IN
BIT_CLK
Note: BIT_CLK not to scale
Slot 11: PCM Right Record Channel
SYNC
Figure 16. STAC9750/9751 Powerdown Timing
fram e
fram e
slot 2
slot 2
per
per
TAG
TAG
29
W rite to
0x20
DATA
PR4
STAC9750/9751
PC AUDIO
V 5.8 103106