IDTSTAC9750XXTAEC1XR IDT, Integrated Device Technology Inc, IDTSTAC9750XXTAEC1XR Datasheet - Page 27

• Manufacturer Part Number: IDTSTAC9750XXTAEC1XR
• Description: IC CODEC AC'97 2CH VALUE 48-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9750XXTAEC1XR

• Resolution (bits): 18 b, 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 85 / 89
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9750XXTAEC1XR

IDT™
VALUE-LINE TWO-CHANNEL AC’97 CODECS
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS
Audio input frame slot 1’s stream echoes the control register index, for historical reference, for the
data to be returned in slot 2. (Assuming that slots 1 and 2 had been tagged “valid” by STAC9750/
9751 during slot 0.)
The first bit (MSB) generated by STAC9750/9751 is always stuffed with a 0. The following 7 bit posi-
tions communicate the associated control register address, and the trailing 12 bit positions are
stuffed with 0 by the STAC9750/9751.
5.1.2.2.
The status data port delivers 16-bit control register read data.
If Slot 2 is tagged “invalid” by STAC9750/9751, then the entire slot will be stuffed with 0's.
5.1.2.3.
Audio input frame slot 3 is the left channel output of STAC9750/9751 input MUX, post-ADC.
STAC9750/9751 ADCs are implemented to support 18-bit resolution.
STAC9750/9751 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0
to fill out its 20-bit time slot.
5.1.2.4.
Audio input frame slot 4 is the right channel output of STAC9750/9751 input MUX, post-ADC.
STAC9750/9751 outputs its ADC data (MSB first), and stuffs any trailing non-valid bit positions with 0
to fill out its 20-bit time slot.
5.1.2.5.
Audio input frame slot 5 is Reserved for modem operation and is not used by the STAC9750/9751.
This slot is always stuffed with 0.
18:12
19:4
11:2
Bit
3:0
1:0
Bit
19
Slot 2: Status Data Port
Slot 3: PCM Record Left Channel
Slot 4: PCM Record Right Channel
Slot 5: Reserved
Control Register Read Data
Reserved
Reserved
Control Register Index
Slot Request
Reserved
Description
Description
Table 13. Status Address Port Bit Assignments
Table 14. Status Data Port Bit Assignments
27
Echo of register index for which data is being returned
Stuffed with 0
see sections below
Stuffed with 0
Stuffed with 0 if tagged “invalid”
Stuffed with 0
STAC9750/9751
Comments
Comments
PC AUDIO
V 5.8 103106