MC68360ZP25L Freescale Semiconductor, MC68360ZP25L Datasheet - Page 601

• Manufacturer Part Number: MC68360ZP25L
• Description: IC MPU QUICC 25MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360ZP25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

The SMCs in UART mode, however, do provide one feature not provided by the regular
SCCs. The SMCs allow a data length option of up to 14 bits; whereas, the SCCs provide a
data length up to 8 bits. See Figure 7-75 for the SMC UART frame format.
7.11.7.3 SMC UART MEMORY MAP. When configured to operate in UART mode, the
QUICC overlays the structure listed in Table 7-5 with the UART-specific parameters
described in Table 7-13.
MAX_IDL. Once a character of data is received on the line, the UART controller begins
counting any idle characters received. If a MAX_IDL number of idle characters is received
before the next data character is received, an idle timeout occurs, and the buffer is closed.
This, in turn, can produce an interrupt request to the CPU32+ core to receive the data from
• Fractional Stop Bits
• Built-In Multidrop Modes
• Freeze Mode for Implementing Flow Control
• Isochronous Operation (1x Clock)
• Interrupts upon Receiving Special Control Characters
• Ability To Transmit Data on Demand using the TODR
• SCCS Register To Determine Idle Status of the Receive Pin
• Other Features for the SCCs as Described in the GSMR
SMTXD
SMCLK
SMC Base + 28
SMC Base + 2A
SMC Base + 2C
SMC Base + 2E
SMC Base +30
SMC Base +32
16
Address
START
BIT
Table 7-13. SMC UART-Specific Parameter RAM
Freescale Semiconductor, Inc.
Figure 7-75. SMC UART Frame Format
For More Information On This Product,
MAX_IDL
R_mask
BRKEC
BRKCR
BRKLN
Name
IDLC
MC68360 USER’S MANUAL
LEAST SIGNIFICANT BIT FIRST
Go to: www.freescale.com
5 TO 14 DATA BITS WITH THE
Width
Word
Word
Word
Word
Word
Word
Maximum Idle Characters
Temporary Idle Counter
Last Received Break Length
Receive Break Condition Counter
Break Count Register (Transmit)
Temporary Bit Mask
Serial Management Controllers (SMCs)
Description
OPTIONAL
PAR.
BIT
(CLOCK NOT TO SCALE)
1 OR 2
STOP BITS