MC68360ZP25L Freescale Semiconductor, MC68360ZP25L Datasheet - Page 510
![IC MPU QUICC 25MHZ 357-PBGA](/photos/6/76/67680/mfg_mpc860_series_sml.jpg)
MC68360ZP25L
Manufacturer Part Number
MC68360ZP25L
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360ZP25L
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
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Serial Communication Controllers (SCCs)
GLt—Glitch on Tx
DCC—DPLL CS Changed
FLG—Flag Status
IDL—Idle Sequence Status Changed
GRA—Graceful Stop Complete
TXE—Tx Error
RXF—Rx Frame
BSY—Busy Condition
TXB—Transmit Buffer
RXB—Receive Buffer
7.10.17.12 HDLC MASK REGISTER (SCCM). The SCCM is referred to as the HDLC mask
register when the SCC is operating as an HDLC controller. It is a 16-bit read-write register
with the same bit formats as the HDLC event register. If a bit in the HDLC mask register is
a one, the corresponding interrupt in the event register will be enabled. If the bit is zero, the
corresponding interrupt in the event register will be masked. This register is cleared upon
reset.
7-186
A clock glitch was detected by this SCC on the transmit clock.
The carrier sense status as generated by the DPLL has changed state. The real-time sta-
tus may be found in SCCS. This is not the CD pin status (which is reported in port C), and
is only valid when the DPLL is used.
The HDLC controller has stopped or started receiving HDLC flags. The real-time status
may be obtained in SCCS.
A change in the status of the serial line was detected on the HDLC line. The real-time sta-
tus of the line may be read in SCCS.
A graceful stop, which was initiated by the GRACEFUL STOP TRANSMIT command, is
now complete. This bit is set as soon the transmitter has finished transmitting any frame
that was in progress when the command was issued. It will be set immediately if no frame
was in progress when the command was issued.
An error (CTS lost or underrun) occurred on the transmitter channel.
A complete frame has been received on the HDLC channel. This bit is set no sooner than
two clocks after receipt of the last bit of the closing flag.
A frame was received and discarded due to lack of buffers.
A buffer has been transmitted on the HDLC channel. This bit is set no sooner than when
the last bit of the closing flag begins its transmission if the buffer is the last one in the
frame. Otherwise, this bit is set after the last byte of the buffer has been written to the
transmit FIFO.
A buffer has been received on the HDLC channel that was not a complete frame.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
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