MC68360ZP25L Freescale Semiconductor, MC68360ZP25L Datasheet - Page 314
![IC MPU QUICC 25MHZ 357-PBGA](/photos/6/76/67680/mfg_mpc860_series_sml.jpg)
MC68360ZP25L
Manufacturer Part Number
MC68360ZP25L
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360ZP25L
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
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System Integration Module (SIM60)
master may generate a bus error as a result of this register, and for parity errors, the PERR
pin may be externally connected to an interrupt input.
Bits 15–9—Reserved
WPER—Write Protect Error
PERx—Parity Error
6.13.3 Base Register (BR)
This register is used for both DRAM and SRAM banks. Most bits are valid for both the DRAM
and SRAM banks, but some bits are only valid for SRAM banks. This register is a 32-bit
read-write register that may be accessed at any time.
V—Valid Bit
6-70
BA31
BA15
31
15
15
0
0
—
This bit is asserted when a write protect error occurs. A bus monitor (BERR assertion) will
(if enabled) prompt the user to read this register if no DSACK is provided on a write cycle.
The accessed address will be in the BERR exception descriptor. WPER is cleared by writ-
ing one to this bit or by performing a system reset. Writing a zero has no effect on WPER.
These bits indicate that a parity error was detected when reading from bank N. BERR is
internally asserted if PBEE in the GMR is set and if an internal master performs this cycle.
The PERR signal is continuously asserted until all PERx bits are cleared. PERx is cleared
by writing one or by performing a system reset. Writing a zero has no effect on PERx.
This bit indicates that the contents of the BR and OR pair are valid. The CS/RAS signal
will not assert until the V-bit is set.
BA30
BA14
30
14
0
0
14
—
BA29
BA13
29
13
0
0
13
—
If external masters of the MC68030-type (including QUICCs) are
chosen to be asynchronous (configured by clearing the SYNC
bit in the GMR), then they have no parity support.
BA28
BA12
28
12
0
0
12
—
BA27
BA11
27
11
0
0
11
—
Freescale Semiconductor, Inc.
For More Information On This Product,
BA26
FC3
26
10
0
0
10
—
MC68360 USER’S MANUAL
BA25
FC2
Go to: www.freescale.com
25
0
9
0
—
9
BA24
FC1
24
0
8
0
WPER
NOTE
8
BA23
FC0
23
0
0
7
PER7
7
TRLXQ BACK40 CSNT40
BA22
22
0
6
1
PER6
6
BA21
21
0
5
0
PER5
5
BA20
20
PER4
0
4
1
4
CSNTQ
BA19
PER3
19
0
3
0
3
PAREN
BA18
PER2
18
2
0
2
0
PER1
BA17
WP
17
1
0
1
0
PER0
BA16
0
16
V
0
0
0
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