MC68EC020FG25 Freescale Semiconductor, MC68EC020FG25 Datasheet - Page 28

• Manufacturer Part Number: MC68EC020FG25
• Description: IC MPU 32 BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020FG25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

1.5.2 Virtual Machine
A typical use for a virtual machine system is the development of software, such as an
operating system, for a new machine also under development and not yet available for
programming use. In a virtual machine system, a governing operating system emulates
the hardware of the new machine and allows the new software to be executed and
debugged as though it were running on the new hardware. Since the new software is
controlled by the governing operating system, it is executed at a lower privilege level than
the governing operating system. Thus, any attempts by the new software to use virtual
resources that are not physically present (and should be emulated) are trapped to the
governing operating system and performed by its software.
In the MC68020/EC020 implementation of a virtual machine, the virtual application runs at
the user privilege level. The governing operating system executes at the supervisor
privilege level and any attempt by the new operating system to access supervisor
resources or execute privileged instructions causes a trap to the governing operating
system.
Instruction continuation is used to support virtual I/O devices in memory-mapped
input/output systems. Control and data registers for the virtual device are simulated in the
memory map. An access to a virtual register causes a fault, and the function of the
register is emulated by software.
1.6 PIPELINED ARCHITECTURE
The MC68020/EC020 contains a three-word instruction pipe where instruction opcodes
are decoded. As shown in Figure 1-5, instruction words (instruction operation words and
all extension words) enter the pipe at stage B and proceed to stages C and D. An
instruction word is completely decoded when it reaches stage D of the pipe. Each stage
has a status bit that reflects whether the word in the stage was loaded with data from a
bus cycle that was terminated abnormally. Stages of the pipe are only filled in response to
specific prefetch requests issued by the sequencer.
Words are loaded into the instruction pipe from the cache holding register. Although the
individual stages of the pipe are only 16 bits wide, the cache holding register is 32 bits
wide and contains the entire long word. This long word is obtained from the instruction
cache or the external bus in response to a prefetch request from the sequencer. When the
sequencer requests an even-word (long-word-aligned) prefetch, the entire long word is
accessed from the instruction cache or the external bus and loaded into the cache holding
register, and the high-order word is also loaded into stage B of the pipe. The instruction
word for the next sequential prefetch can then be accessed directly from the cache
holding register, and no external bus cycle or instruction cache access is required. The
cache holding register provides instruction words to the pipe regardless of whether the
instruction cache is enabled or disabled.
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M68020 USER’S MANUAL
MOTOROLA