MC68EC020FG25 Freescale Semiconductor, MC68EC020FG25 Datasheet - Page 132

• Manufacturer Part Number: MC68EC020FG25
• Description: IC MPU 32 BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020FG25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

instruction, the vector number is 32 plus n. The stack frame saves the trap vector offset,
the PC, and the internal copy of the SR on the supervisor stack. The saved value of the
PC is the logical address of the instruction following the instruction that caused the trap.
For all instruction traps other than TRAP, a pointer to the instruction that caused the trap
is also saved. Instruction execution resumes at the address in the exception vector after
the required instruction prefetches.
6.1.5 Illegal Instruction and Unimplemented Instruction Exceptions
An illegal instruction is an instruction that contains any bit pattern in its first word that does
not correspond to the bit pattern of the first word of a valid MC68020/EC020 instruction or
a MOVEC instruction with an undefined register specification field in the first extension
word. An illegal instruction exception corresponds to vector number 4 and occurs when
the processor attempts to execute an illegal instruction.
An illegal instruction exception is also taken if a breakpoint acknowledge bus cycle (see
Section 5 Bus Operation) is terminated with the assertion of the BERR signal. This
implies that the external circuitry did not supply an instruction word to replace the BKPT
instruction word in the instruction pipe.
Instruction word patterns with bits 15–12 = 1010 are referred to as unimplemented
instructions with A-line opcodes. When the processor attempts to execute an
unimplemented instruction with an A-line opcode, an exception is generated with vector
number 10, permitting efficient emulation of unimplemented instructions.
Instructions that have word patterns with bits 15–12 = 1111, bits 11–9 = 000, and defined
word patterns for subsequent words, are legal PMMU instructions. Instructions that have
bits 15–12 of the first words = 1111, bits 11–9 = 000, and undefined patterns in the
subsequent words, are treated as unimplemented instructions with F-line opcodes when
execution is attempted in the supervisor privilege level. When execution of the same
instruction is attempted in the user privilege level, a privilege violation exception is taken.
The exception vector number for an unimplemented instruction with an F-line opcode is
11.
The word patterns with bits 15–12 = 1111 and bits 11–9
000 are used for coprocessor
instructions. When the processor identifies a coprocessor instruction, it runs a bus cycle
referencing CPU space type $2 (refer to Section 2 Processing States) and addressing
one of eight coprocessors (0–7, according to bits 11–9). If the addressed coprocessor is
not included in the system and the cycle terminates with the assertion of BERR , the
instruction takes an unimplemented instruction (F-line opcode) exception. The system can
emulate the functions of the coprocessor with an F-line exception handler. Refer to
Section 7 Coprocessor Interface Description for more details.
MOTOROLA
M68020 USER’S MANUAL
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