MC68EC020FG25 Freescale Semiconductor, MC68EC020FG25 Datasheet - Page 178

• Manufacturer Part Number: MC68EC020FG25
• Description: IC MPU 32 BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020FG25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

After writing the format word to the restore CIR, the main processor continues
cpRESTORE dialog by reading that same register. If the coprocessor returns a valid
format word, the main processor transfers the number of bytes specified by the format
word at the effective address to the operand CIR.
If the format word written to the restore CIR does not represent a valid coprocessor state
frame, the coprocessor places an invalid format word in the restore CIR and terminates
any current operations. The main processor receives the invalid format code, writes an
abort mask (refer to 7.2.3.2.3 Invalid Format Word) to the control CIR, and initiates
format error exception processing (refer to 7.5.1.5 Format Errors).
The cpRESTORE instruction is a privileged instruction. When the MC68020/EC020
accesses a cpRESTORE instruction, it checks the S-bit in the SR. If the MC68020/EC020
attempts to execute a cpRESTORE instruction while at the user privilege level (S-bit in the
SR is clear), it initiates privilege violation exception processing without accessing any of
the CIRs (refer to 7.5.2.3 Privilege Violations).
7.3 COPROCESSOR INTERFACE REGISTER SET
The instructions of the M68000 coprocessor interface use registers of the CIR set to
communicate with the coprocessor. These CIRs are not directly related to the coprocessor
programming model.
Figure 7-4 is a memory map of the CIR set. The response, control, save, restore,
command, condition, and operand registers must be included in a coprocessor interface
that implements all four coprocessor instruction categories. The complete register model
must be implemented if the system uses all coprocessor response primitives defined for
the M68000 coprocessor interface.
The following paragraphs contain detailed descriptions of the registers.
7.3.1 Response CIR
The coprocessor uses the 16-bit response CIR to communicate all service requests
(coprocessor response primitives) to the main processor. The main processor reads the
response CIR to receive the coprocessor response primitives during the execution of
instructions in the general and conditional instruction categories. The offset from the base
address of the CIR set for the response CIR is $00. Refer to 7.4 Coprocessor Response
Primitives for additional information.
7.3.2 Control CIR
The main processor writes to the 2-bit control CIR to acknowledge coprocessor-requested
exception processing or to abort the execution of a coprocessor instruction. The offset
from the base address of the CIR set for the control CIR is $02. The control CIR occupies
the two least significant bits of the word at that offset. The 14 most significant bits of the
word are undefined and reserved by Motorola. Figure 7-19 shows the format of this
register.
MOTOROLA
M68020 USER’S MANUAL
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