MC68EC020FG25 Freescale Semiconductor, MC68EC020FG25 Datasheet - Page 169

• Manufacturer Part Number: MC68EC020FG25
• Description: IC MPU 32 BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020FG25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

If the coprocessor requires additional information to evaluate the condition, the cpDBcc
instruction can include this information in extension words. These extension words follow
the word containing the coprocessor condition selector field in the cpDBcc instruction
format.
The last word of the instruction contains the displacement for the cpDBcc instruction. This
displacement is a twos-complement 16-bit value that is sign-extended to long-word size
when it is used in a destination address calculation.
7.2.2.3.2 Protocol. Figure 7-8 shows the protocol for the cpDBcc instructions. The
MC68020/EC020 transfers the condition selector to the coprocessor by writing the word
following the operation word to the condition CIR. The main processor then reads the
response CIR to determine its next action. The coprocessor can use a response primitive
to request any services necessary to evaluate the condition. If the coprocessor returns the
true condition indicator, the main processor executes the next instruction in the instruction
stream. If the coprocessor returns the false condition indicator, the main processor
decrements the low-order word of the register specified by bits 2–0 of the F-line operation
word. If this register contains minus one (–1) after being decremented, the main processor
executes the next instruction in the instruction stream. If the register does not contain
minus one (–1) after being decremented, the main processor branches to the destination
address to continue instruction execution.
The MC68020/EC020 adds the displacement to the scanPC (refer to 7.4.1 ScanPC) to
determine the address of the next instruction. The scanPC must point to the 16-bit
displacement in the instruction stream when the destination address is calculated.
7.2.2.4 TRAP ON COPROCESSOR CONDITION INSTRUCTION. The trap on
coprocessor condition instruction allows the programmer to initiate exception processing
based on conditions related to the coprocessor operation.
7.2.2.4.1 Format. Figure 7-13 shows the format of the trap on coprocessor condition
instruction, denoted by the cpTRAPcc mnemonic.
The first word of the cpTRAPcc instruction, the F-line operation word contains the CpID
field in bits 11–9 and 001111 in bits 8–3 to identify the cpTRAPcc instruction. Bits 2–0 of
the cpTRAPcc F-line operation word specify the opmode, which selects the instruction
format. The instruction format can include zero, one, or two operand words.
7-16
15
1
14
1
13
1
Figure 7-13. Trap on Coprocessor Condition
12
1
(RESERVED)
OPTIONAL COPROCESSOR-DEFINED EXTENSION WORDS
11
Instruction Format (cpTRAPcc)
CpID
M68020 USER’S MANUAL
OR LONG-WORD OPERAND
9
OPTIONAL WORD
0
8
0
7
6
1
5
5
1
4
1
CONDITION SELECTOR
1
3
2
OPMODE
MOTOROLA
0