MC68EC020FG25 Freescale Semiconductor, MC68EC020FG25 Datasheet - Page 129

• Manufacturer Part Number: MC68EC020FG25
• Description: IC MPU 32 BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020FG25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

6.1.1 Reset Exception
Assertion of the RESET signal by external hardware causes a reset exception. For details
on the requirements for the assertion of RESET , refer to Section 5 Bus Operation.
The reset exception has the highest priority of any exception; it provides for system
initialization and recovery from catastrophic failure. When a reset exception is recognized,
it aborts any processing in progress and that processing cannot be recovered. Figure 6-1
is a flowchart of the reset exception, which performs the following operations:
After the initial instruction prefetches, program execution begins at the address in the PC.
The reset exception does not save the value of either the PC or the SR.
As described in Section 5 Bus Operation, if a bus error or address error occurs during
the exception processing sequence for a reset, a double bus fault occurs. The processor
halts and asserts the HALT signal to indicate the halted condition.
Execution of the RESET instruction does not cause a reset exception, nor does it affect
any internal registers, but it does cause the MC68020/EC020 to assert the RESET signal,
resetting all external devices.
6.1.2 Bus Error Exception
A bus error exception occurs when external logic aborts a bus cycle by asserting the
BERR signal. If the aborted bus cycle is a data access, the processor immediately begins
exception processing. If the aborted bus cycle is an instruction prefetch, the processor
may delay taking the exception until it attempts to use the prefetched information.
6-4
1. Clears the T1 and T0 bits in the SR to disable tracing.
2. Places the processor in the interrupt mode of the supervisor privilege level by setting
3. Sets the I2–I0 bits in the SR to the highest priority level (level 7).
4. Initializes the VBR to zero ($00000000).
5. Clears the E and F bits in the CACR.
6. Invalidates all entries in the instruction cache.
7. Generates a vector number to reference the reset exception vector (two long words)
8. Loads the first long word of the reset exception vector into the interrupt stack pointer.
9. Loads the second long word of the reset exception vector into the PC.
the S-bit and clearing the M-bit in the SR.
at offset zero in the supervisor program address space.
M68020 USER’S MANUAL
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