MC68EC020FG25 Freescale Semiconductor, MC68EC020FG25 Datasheet - Page 133

• Manufacturer Part Number: MC68EC020FG25
• Description: IC MPU 32 BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020FG25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Exception processing for illegal and unimplemented instructions is similar to that for
instruction traps. When the processor has identified an illegal or unimplemented
instruction, it initiates exception processing instead of attempting to execute the
instruction. The processor copies the SR, enters the supervisor privilege level (by setting
the S bit in the SR), and clears the T1 and T0 bits in the SR, disabling further tracing. The
processor generates the vector number, either 4, 10, or 11, according to the exception
type. The illegal or unimplemented instruction vector offset, current PC, and copy of the
SR are saved on the supervisor stack, with the saved value of the PC being the address
of the illegal or unimplemented instruction. Instruction execution resumes at the address
contained in the exception vector. It is the responsibility of the handling routine to adjust
the stacked PC if the instruction is emulated in software or is to be skipped on return from
the handler.
6.1.6 Privilege Violation Exception
To provide system security, the following instructions are privileged:
An attempt to execute one of the privileged instructions while at the user privilege level
causes a privilege violation exception. Also, a privilege violation exception occurs if a
coprocessor requests a privilege check and the processor is at the user level.
Exception processing for privilege violations is similar to that for illegal instructions. When
the processor identifies a privilege violation, it begins exception processing before
executing the instruction. The processor copies the SR, enters the supervisor privilege
level by setting the S-bit in the SR, and clears the T1 and T0 bits in the SR. The processor
generates vector number 8, the privilege violation exception vector, and saves the
privilege violation vector offset, the current PC value, and the internal copy of the SR on
the supervisor stack. The saved value of the PC is the logical address of the first word of
the instruction that caused the privilege violation. Instruction execution resumes after the
required prefetches from the address in the privilege violation exception vector.
6-8
ANDI to SR
EORI to SR
cpRESTORE
cpSAVE
MOVE from SR
MOVE to SR
MOVE USP
MOVEC
MOVES
ORI to SR
RESET
RTE
STOP
M68020 USER’S MANUAL
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