FW80960VH100 Intel, FW80960VH100 Datasheet - Page 4

• Manufacturer Part Number: FW80960VH100
• Description: IC MPU I960VH 3V 100MHZ 324-BGA
• Manufacturer: Intel

Specifications of FW80960VH100

• Rohs Status: RoHS non-compliant
• Processor Type: i960
• Features: VH suffix, 32-Bit, 16K Cache
• Speed: 100MHz
• Voltage: 3V
• Mounting Type: Surface Mount
• Package / Case: 324-BGA
• Other names: 820682

80960VH
5.0
6.0
Figures
4
Bus Functional Waveforms .............................................................................................. 54
Device Identification On Reset ......................................................................................... 63
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Product Name Functional Block Diagram ............................................................. 8
80960JT Core Block Diagram ............................................................................. 10
324-Plastic Ball Grid Array Top and Side View ................................................... 25
324-Plastic Ball Grid Array (Top View)................................................................ 26
Thermocouple Attachment .................................................................................. 33
V
V
AC Test Load ...................................................................................................... 44
P_CLK, TCLK Waveform .................................................................................... 45
T
T
T
T
DT/R# and DEN# Timings Waveform ................................................................. 47
I
Fast Page-Mode Read Access, Non-Interleaved, 2,1,1,1 Wait State, 32-Bit 80960
Local Bus ............................................................................................................ 48
Fast Page-Mode Write Access, Non-Interleaved, 2,1,1,1 Wait States, 32-Bit 80960
Local Bus ............................................................................................................ 49
FPM DRAM System Read Access, Interleaved, 2,0,0,0 Wait States.................. 50
FPM DRAM System Write Access, Interleaved, 1,0,0,0 Wait States .................. 51
EDO DRAM, Read Cycle .................................................................................... 52
EDO DRAM, Write Cycle .................................................................................... 52
32-Bit Bus, SRAM Read Accesses with 0 Wait States ....................................... 53
32-Bit Bus, SRAM Write Accesses with 0 Wait States........................................ 53
Non-Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local
Bus ...................................................................................................................... 54
Burst Read and Write Transactions without Wait States, 32-Bit 80960
Local Bus ............................................................................................................ 55
Burst Write Transactions with 2,1,1,1 Wait States, 32-Bit 80960 Local Bus ....... 56
Burst Read and Write Transactions without Wait States, 8-Bit 80960 Local Bus57
Burst Read and Write Transactions with 1, 0 Wait States and Extra Tr State on
Read, 16-Bit 80960 Local Bus ............................................................................ 58
Bus Transactions Generated by Double Word Read Bus Request, Misaligned One
Byte From Quad Word Boundary, 32-Bit 80960 Local Bus................................. 59
HOLD/HOLDA Waveform For Bus Arbitration .................................................... 60
80960 Core Cold Reset Waveform ..................................................................... 61
80960 Local Bus Warm Reset Waveform ........................................................... 62
2
OV
OF
IS
LXL
CC5
CCPLL
C Interface Signal Timings................................................................................ 47
and T
Output Float Waveform................................................................................ 46
Output Delay Waveform .............................................................................. 45
and T
Current-Limiting Resistor ........................................................................... 36
Lowpass Filter ........................................................................................ 36
IH
LXA
Input Setup and Hold Waveform ...................................................... 46
Relative Timings Waveform ........................................................ 46
Preliminary
Datasheet