FW80960VH100 Intel, FW80960VH100 Datasheet - Page 15

• Manufacturer Part Number: FW80960VH100
• Description: IC MPU I960VH 3V 100MHZ 324-BGA
• Manufacturer: Intel

Specifications of FW80960VH100

• Rohs Status: RoHS non-compliant
• Processor Type: i960
• Features: VH suffix, 32-Bit, 16K Cache
• Speed: 100MHz
• Voltage: 3V
• Mounting Type: Surface Mount
• Package / Case: 324-BGA
• Other names: 820682

3.0
3.1
3.1.1
Preliminary Datasheet
Table 3.
Package Information
Package Introduction
The 80960VH is offered in a Plastic Ball Grid Array (PBGA) package. This is a perimeter array
package with five rows of ball connections in the outer area of the package. See
Section 3.1.1, Functional Signal Definitions
PBGA Package
Functional Signal Definitions
Table 3
signals associated with the bus interface.
test functions.
signals.
10
Signal Type Definition
defines clock signals.
Symbol
S (...)
A (...)
R (...)
OD
presents the legend for interpreting the Type Field in the following tables.
I/O
Table 8
O
–
I
Table 6
defines the signal and ball locations.
defines Memory Controller signals.
Input signal only.
Output signal only.
Signal can be either an input or output.
Open Drain signal.
Signal must be connected as described.
Synchronous. Inputs must meet setup and hold times relative to P_CLK.
S(E) Edge sensitive input
S(L) Level sensitive input
Asynchronous. Inputs may be asynchronous relative to P_CLK.
A(E) Edge sensitive input
A(L) Level sensitive input
While the P_RST# signal is asserted, the signal:
R(1) is driven to V
R(0) is driven to V
R(Q) is a valid output
R(Z) Floats
R(H) is pulled up to V
R(X) is driven to an unknown state
defines signals associated with the Interrupt Unit.
CC
SS
CC
Table 5
describes signal function.
defines signals associated with basic control and
Table 9
Description
defines DMA, and I
Section 3.1.2, 324-Lead
Table 7
Figure , (pg.
2
defines PCI
C signals.
Table 4
80960VH
defines
Table
26).
15