FW80960VH100 Intel, FW80960VH100 Datasheet
FW80960VH100
Specifications of FW80960VH100
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FW80960VH100 Summary of contents
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... Four Message Registers — Two Doorbell Registers Notice: This document contains preliminary information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. Preliminary ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel’s website at http://www.intel.com. ...
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Contents 1.0 About This Document......................................................................................................... 7 1.1 Solutions960 1.2 Terminology........................................................................................................... 7 1.3 Additional Information Sources ............................................................................. 7 2.0 Functional Overview........................................................................................................... 8 2.1 Key Functional Units ............................................................................................. 9 2.1.1 DMA Controller......................................................................................... 9 2.1.2 Address Translation Unit .......................................................................... 9 2.1.3 Messaging Unit......................................................................................... ...
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Bus Functional Waveforms .............................................................................................. 54 6.0 Device Identification On Reset ......................................................................................... 63 Figures 1 Product Name Functional Block Diagram ............................................................. 8 2 80960JT Core Block Diagram ............................................................................. 10 3 324-Plastic Ball Grid Array Top and Side View ................................................... ...
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Tables 1 Related Documentation......................................................................................... 7 2 80960VH Instruction Set .....................................................................................14 3 Signal Type Definition ......................................................................................... 15 4 Signal Descriptions.............................................................................................. 16 5 Power Requirement, Processor Control and Test Signal Descriptions ............... 19 6 Interrupt Unit Signal Descriptions........................................................................ 20 7 PCI Signal ...
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... About This Document This is the Preliminary data sheet for the low-power (3.3 V) version of Intel’s i960 (“80960VH”) family. This data sheet contains a functional overview, mechanical data (package signal locations and simulated thermal characteristics), targeted electrical specifications (simulated), and bus functional waveforms. Detailed functional descriptions other than parametric performance is published in the ® ...
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Functional Overview As indicated in Figure highly integrated processor. Subsections following the figure briefly describe the main features; for detailed functional descriptions, refer to the i960 The PCI bus is an industry standard, high performance, low latency system ...
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Key Functional Units 2.1.1 DMA Controller The DMA Controller supports low-latency, high-throughput data transfers between PCI bus agents and 80960 local memory. Two separate DMA channels accommodate data transfers for the primary PCI bus. The DMA Controller supports chaining ...
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Core Features (80960JT) The processing power of the 80960VH comes from the 80960JT processor core. The 80960JT is a new, scalar implementation of the 80960 Core Architecture. 80960JT Core processor. Factors that contribute to the 80960 ...
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Burst Bus A 32-bit high-performance bus controller interfaces the 80960VH to external memory and peripherals. The Bus Control Unit fetches instructions and transfers data on the local bus at the rate four 32-bit words per six ...
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The processor also has built-in debug capabilities. Via software, the 80960VH may be configured to detect as many as seven different trace event types. Alternatively, mark and fmark instructions can generate trace events explicitly in the instruction stream. Hardware ...
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Instructions, Data Types and Memory Addressing Modes As with all 80960 family processors, the 80960VH instruction set supports several different data types and formats: • Bit • Bit fields • Integer (8-, 16-, 32-, 64-bit) • Ordinal (8-, 16-, ...
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Table 2. 80960VH Instruction Set Data Movement Load Store Move Conditional Select Load Address Comparison Compare Conditional Compare Compare and Increment Compare and Decrement Test Condition Code Check Bit Debug Modify Trace Controls Mark Force Mark 14 Arithmetic Logical ...
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Package Information 3.1 Package Introduction The 80960VH is offered in a Plastic Ball Grid Array (PBGA) package. This is a perimeter array package with five rows of ball connections in the outer area of the package. See Section 3.1.1, ...
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Table 3. Signal Type Definition Symbol H (...) P (...) K (...) Table 4. Signal Descriptions (Sheet NAME AD31:0 ADS# ALE BLAST# 16 Description While the is in the hold state, the signal: H(1) is driven ...
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Table 4. Signal Descriptions (Sheet NAME BE3:0# DEN# D/C#/ RST_MODE# DT/R# Preliminary Datasheet TYPE BYTE ENABLES select which four data bytes on the bus participate in the current bus access. Byte enable encoding depends ...
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Table 4. Signal Descriptions (Sheet NAME LOCK#/ONCE# LRDYRCV#/ STEST HOLD HOLDA RDYRCV# 18 TYPE BUS LOCK indicates that an atomic read-modify-write operation is in progress. The LOCK# output is asserted in the first clock of an ...
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Table 4. Signal Descriptions (Sheet NAME W/R# WIDTH/ HLTD0 WIDTH/ HLTD1/ RETRY Table 5. Power Requirement, Processor Control and Test Signal Descriptions (Sheet NAME FAIL# L_RST# TCK TDI Preliminary Datasheet TYPE WRITE/READ specifies during ...
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Table 5. Power Requirement, Processor Control and Test Signal Descriptions (Sheet NAME TDO TMS TRST# LCDINIT REF CC5 V SS N.C. VCCPLL2:1 20 TYPE DESCRIPTION O TEST DATA OUTPUT is the serial output ...
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Table 6. Interrupt Unit Signal Descriptions NAME NMI# XINT3:0# XINT7:4# NOTE: PCI signal functions are summarized in this data sheet. Refer to the 1. a more complete definition. Table 7. PCI Signal Descriptions (Sheet NAME P_AD31:0 P_C/BE3:0# ...
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Table 7. PCI Signal Descriptions (Sheet NAME P_LOCK# P_PAR P_PERR# P_REQ# P_RST# P_SERR# P_STOP# P_TRDY# NOTE: PCI signal functions are summarized in this data sheet; refer to the 1. a more complete definition. 22 TYPE I ...
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Table 8. Memory Controller Signal Descriptions (Sheet NAME CAS7:0# CE1:0# DALE1:0 DP3:0 DWE1:0# LEAF1:0# Preliminary Datasheet TYPE DESCRIPTION COLUMN ADDRESS STROBE signals are used for DRAM accesses and are asserted when the MA11:0 signals contain a valid ...
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Table 8. Memory Controller Signal Descriptions (Sheet NAME MA11:0 MWE3:0# RAS3:0# 2 Table 9. DMA Units Signal Descriptions NAME DACK# DREQ# SCL SDA WAIT# 24 TYPE MULTIPLEXED ADDRESS signals are multi-purpose depending on the ...
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Table 10. Clock Related Signals NAME P_CLK CLKMODE1:0# Preliminary Datasheet TYPE SYNCHRONOUS PCI BUS CLOCK Provides the timing for all primary PCI I transactions and is the clock source for all internal units. All input/output timings are relative to P_CLK. ...
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PBGA Package Figure 3. 324-Plastic Ball Grid Array Top and Side View Pin #1 Corner Pin #1 I.D. Note: All Dimensions are in Millimeters 30˚ Top ...
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Figure 4. 324-Plastic Ball Grid Array (Top View) Pin #1 Corner b e 325 Balls Matrix 1.0 3 places Table 11. PBGA 324 Package Dimensions balls D ...
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Table 12. 324-Plastic Ball Grid Array Ballout — In Ball Order (Sheet Ball Signal WAIT# A3 P_AD3 P_C/BE0 P_AD10 P_AD13 ...
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Table 12. 324-Plastic Ball Grid Array Ballout — In Ball Order (Sheet Ball Signal B11 MA4 MA8 H16 P_INTC# H17 V SS H18 P_INTB# ...
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Table 12. 324-Plastic Ball Grid Array Ballout — In Ball Order (Sheet Ball Signal K10 WIDTH/HLTD0 U10 V CC U11 V ...
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Table 13. 324-Plastic Ball Grid Array Ballout — In Signal Order (Sheet Signal Ball AD0 V11 AD1 Y11 AD2 V12 AD3 W12 AD4 Y12 AD5 V13 AD6 T13 AD7 Y13 AD8 V14 AD9 U14 AD10 Y16 AD11 ...
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Table 13. 324-Plastic Ball Grid Array Ballout — In Signal Order (Sheet Signal Ball P_AD2 D5 P_AD3 A3 P_AD4 C5 P_AD5 B5 P_AD6 C6 P_AD7 D7 P_AD8 C7 P_AD9 B7 P_AD10 A7 P_AD11 C8 P_AD12 B9 ...
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Table 13. 324-Plastic Ball Grid Array Ballout — In Signal Order (Sheet Signal Ball V C20 T12 CC VCC5REF P20 VCCPLL1 Y10 VCCPLL2 G20 A15 ...
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Package Thermal Specifications The device is specified for operation when T 95° C. Case temperature may be measured in any environment to determine whether the processor is within specified operating range. Measure the case temperature at the center ...
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Thermal Resistance The thermal resistance value for the case-to-ambient, solution’s thermal performance. 3.2.2 Thermal Analysis Table 14 lists the case-to-ambient thermal resistances of the 80960VH for different air flow rates without a heat sink. To calculate T , the ...
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... NOTE: 1. The 80960VH processor is produced on Intel’s advanced CMOS process. Proper bulk decoupling must be used to prevent device damage during power up and power down. Power supply behavior during these transitions, without proper bulk decoupling, can cause the power supply to exceed the maximum V specification, causing device damage ...
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Figure 6. V Current-Limiting Resistor CC5 This resistor is not necessary in systems that can guarantee the V In 3.3 V-only systems and systems that drive 80960VH pins from 3.3 V logic, connect the V pin directly to the 3.3 ...
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DC Specifications Table 18. DC Characteristics Symbol V Input Low Voltage IL Input High Voltage for all signals V IH1 except P_CLK V Output Low Voltage Processor signals OL1 V Output High Voltage Processor signals OH1 V Output ...
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Table 19. I Characteristics CC Symbol Input Leakage Current for each signal except PCI Bus Signals, LOCK#/ONCE#, WIDTH/ HLTD0, WIDTH/HLTD1/RETRY, BLAST#, I LI1 D/C#/RST_MODE#, DEN#, TMS, TRST#, Input Leakage Current for LOCK#/ONCE#, I BLAST#, D/C#/RST_MODE#, DEN#, TMS, LI2 Input Leakage ...
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AC Specifications Table 20. Input Clock Timings Symbol T P_CLK Frequency F T P_CLK Period C T P_CLK Period Stability CS T P_CLK High Time CH T P_CLK Low Time CL T P_CLK Rise Time CR T P_CLK ...
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Table 22. Synchronous Input Timings Sym T Input Setup to P_CLK — NMI#, XINT7:0#, DP3:0 IS1 Input Setup to P_CLK — for all accesses except Expansion ROM T IS1A Accesses — AD31:0 only Input Setup to P_CLK during Expansion ROM ...
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Relative Output Timings Table 23. Relative Output Timings Symbol T ALE Width LXL T Address Hold from ALE Inactive LXA T DT/R# Valid to DEN# Active DXD NOTES: 1. Guaranteed by design. May not be 100% tested. 2. ...
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Table 25. Fast Page Mode Interleaved DRAM Output Timings (Sheet Symbol T DALE1:0 Initial Falling Edge Output Valid Delay OV18 T DALE1:0 Burst Falling Edge Output Valid Delay OV19 T DALE1:0 Rising Edge Output Valid Delay OV20 ...
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Table 27. SRAM/ROM Output Timings (Sheet Symbol T MA11:0 Output Valid Delay - Initial Address OV43 T MA11:0 Output Valid Delay - Burst Address OV44 NOTES: 1. Signal generated on the rising edge of an internally ...
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I C Interface Signal Timings 2 Table 29 Interface Signal Timings Symbol F SCL Clock Frequency SCL Bus Free Time Between STOP and START T BUF Condition T Hold Time (repeated) START Condition HDSTA T SCL ...
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AC Timing Waveforms Figure 9. P_CLK, TCLK Waveform T Figure 10. T Output Delay Waveform 1.5V P_CLK 1.5V Max T OVX 1.5V Valid 2.0V 1.5V 0.8V T ...
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Figure 11. T Output Float Waveform OF P_CLK Figure 12. T and T Input Setup and Hold Waveform IS IH P_CLK Figure 13. T and T Relative Timings Waveform LXL LXA Preliminary Datasheet 1. ...
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Figure 14. DT/R# and DEN# Timings Waveform P_CLK DT/R# DEN# 2 Figure 15 Interface Signal Timings SDA T BUF SCL Stop 1.5V T OVX T DXD T T LOW ...
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Memory Controller Output Timing Waveforms Figure 16. Fast Page-Mode Read Access, Non-Interleaved, 2,1,1,1 Wait State, 32-Bit 80960 Local Bus P_CLK AD31:0 MA11:0 ALE ADS# W/R# BLAST# DT/R# DEN# DWE0# RAS0# CAS3:0# LRDYRCV# RDYRCV# Preliminary Datasheet ...
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Figure 17. Fast Page-Mode Write Access, Non-Interleaved, 2,1,1,1 Wait States, 32-Bit 80960 Local Bus P_CLK AD31:0 MA11:0 ALE ADS# BE3:0# W/R# BLAST# DT/R# MWE0# DWE0# RAS0# CAS3:0# LRDYRCV# RDYRCV ...
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Figure 18. FPM DRAM System Read Access, Interleaved, 2,0,0,0 Wait States P_CLK AD[31:0] RAS[n]# RAS[n+1#] MA[11:0] DALE[0]# CAS[3:0]# LEAF[0]# DALE[1]# CAS[7:4]# LEAF[1]# DWE[1:0]# Preliminary Datasheet ...
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Figure 19. FPM DRAM System Write Access, Interleaved, 1,0,0,0 Wait States P_CLK AD[31:0] RAS[n]# RAS[n+1]# MA[11:0] DALE[0]# CAS[3:0]# LEAF[0]# DALE[1]# CAS[7:4]# LEAF[1]# DWE[1:0 DATA DATA DATA ADDR OUT ...
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Figure 20. EDO DRAM, Read Cycle P_CLK RAS# MA[11:0] CAS# AD[31:0] Figure 21. EDO DRAM, Write Cycle P_CLK RAS# MA[11:0] CAS# AD[31:0] Preliminary Datasheet COL COL ROW COL D D ...
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Figure 22. 32-Bit Bus, SRAM Read Accesses with 0 Wait States MWE[3:0]# Figure 23. 32-Bit Bus, SRAM Write Accesses with 0 Wait States MWE[3:0 P_CLK CE[1]# ADDR ADDR ADDR ADDR ...
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Bus Functional Waveforms Figure 24. Non-Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local Bus P_CLK AD31:0 ALE ADS# BE3:0# WIDTH1:0 D/C# W/R# BLAST# DT/R# DEN# LRDYRCV# RDYRCV# Preliminary Datasheet ...
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Figure 25. Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local Bus P_CLK AD31:0 ALE ADS# BE3:0# WIDTH1:0 D/C# W/R# BLAST# DT/R# DEN# LRDYRCV# RDYRCV ...
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Figure 26. Burst Write Transactions with 2,1,1,1 Wait States, 32-Bit 80960 Local Bus P_CLK AD31:0 ALE ADS# BE3:0# WIDTH1:0 D/C# W/R# BLAST# DT/R# DEN# LRDYRCV# RDYRCV# Preliminary Datasheet ...
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Figure 27. Burst Read and Write Transactions without Wait States, 8-Bit 80960 Local Bus P_CLK AD31:0 ALE ADS# BE1/A1# BE0/A0# WIDTH1:0 D/C# W/R# BLAST# DT/R# DEN# LRDYRCV# RDYRCV ...
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Figure 28. Burst Read and Write Transactions with 1, 0 Wait States and Extra Tr State on Read, 16-Bit 80960 Local Bus P_CLK AD31:0 ALE ADS# BE1/A1# BE3# BE0# WIDTH1:0 D/C# W/R# BLAST# DT/R# DEN# LRDYRCV# RDYRCV# Preliminary Datasheet T ...
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Figure 29. Bus Transactions Generated by Double Word Read Bus Request, Misaligned One Byte From Quad Word Boundary, 32-Bit 80960 Local Bus P_CLK AD31:0 ALE ADS# BE3:0# WIDTH1:0 D/C# W/R# BLAST# DT/R# DEN# LRDYRCV# RDYRCV ...
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Figure 30. HOLD/HOLDA Waveform For Bus Arbitration ALE, ADS#, BE3:0# D/C#/RSTMODE# LRDYRCV#, FAIL# WIDTH/HLTD1, WIDTH/HLTD1/RETRY, W/R#, DT/R#, DEN#, BLAST#, LOCK#/ONCE# NOTE: HOLD is sampled on the rising edge of P_CLK. HOLDA is granted after the latency counter in the local ...
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Datasheet Preliminary Waveform Reset Cold Core 80960 62 31. Figure 80960VH ...
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Figure 32. 80960 Local Bus Warm Reset Waveform Preliminary Datasheet 80960VH 63 ...
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... ID MMRs. One holds the Processor Device ID (PDIDR - 0000 1710H) and the other holds the i960 Core Processor Device ID (DEVICEID - FF00 8710H). During initialization, the PDIDR is placed in g0. The device identification values are compliant with the IEEE 1149.1 specification and Intel standards. Table 30 Table 30 ...