FW80960VH100 Intel, FW80960VH100 Datasheet - Page 16

• Manufacturer Part Number: FW80960VH100
• Description: IC MPU I960VH 3V 100MHZ 324-BGA
• Manufacturer: Intel

Specifications of FW80960VH100

• Rohs Status: RoHS non-compliant
• Processor Type: i960
• Features: VH suffix, 32-Bit, 16K Cache
• Speed: 100MHz
• Voltage: 3V
• Mounting Type: Surface Mount
• Package / Case: 324-BGA
• Other names: 820682

80960VH
16
Table 3.
Table 4.
Signal Type Definition
Signal Descriptions (Sheet 1 of 4)
AD31:0
ADS#
ALE
BLAST#
Symbol
NAME
H (...)
P (...)
K (...)
While the is in the hold state, the signal:
H(1) is driven to V
H(0) is driven to V
H(Q) Maintains previous state or continues to be a valid output
H(Z) Floats
While the 80960VH is halted, the signal:
P(1) is driven to V
P(0) is driven to V
P(Q) Maintains previous state or continues to be a valid output
While the PCI Bus is in park mode, the pin:
K(Z) Floats
K(Q) Maintains previous state or continues to be a valid output
TYPE
P(Q)
R(H)
S(L)
R(Z)
H(Z)
R(1)
H(Z)
P(1)
R(0)
H(Z)
P(0)
H(Z)
P(1)
I/O
O
O
O
ADDRESS / DATA BUS carries 32-bit physical addresses and 8-, 16- or 32-
bit data to and from memory. During an address (
physical word address (bits 0-1 indicate SIZE; see below). During a data (T
cycle, read or write data is present on one or more contiguous bytes,
comprising AD31:24, AD23:16, AD15:8 and AD7:0. During write operations,
unused signals are driven to determinate values.
SIZE, which comprises bits 0-1 of the AD lines during a
number of data transfers during the bus transaction on the local bus.
When the DMA or ATUs initiate data transfers, transfer size shown below is
not valid.
When the 80960VH enters Halt mode and the previous bus operation was:
Typically, AD1:0 reflect the SIZE information of the last bus transaction (either
instruction fetch or load/store) that was executed before entering Halt mode.
ADDRESS STROBE indicates a valid address and the start of a new bus
access. The processor asserts ADS# for the entire
control logic typically samples ADS# at the end of the cycle.
ADDRESS LATCH ENABLE indicates the transfer of a physical address.
ALE is asserted during a
T
cycle (T
BURST LAST indicates the last transfer in a bus access. BLAST# is asserted
in the last data transfer of burst and non-burst accesses. BLAST# remains
active while wait states are detected via the LRDYRCV# or RDYRCV# signal
on the memory controller. BLAST# becomes inactive after the final data
transfer in a bus cycle. BLAST# has a weak internal pullup which is active
during reset to ensure normal operation when the signal is not connected.
0 = Last Data Transfer
1 = Not the Last Data Transfer
• write — AD31:2 are driven with the last data value on the AD bus.
• read — AD31:2 are driven with the last address value on the AD bus.
d
state. It is active HIGH and floats to a high impedance state during a hold
AD1
0
0
1
1
CC
SS
CC
SS
h
).
AD0
0
1
0
1
T
a
Description
cycle and deasserted before the beginning of the
DESCRIPTION
Bus Transfers
1 Transfer
2 Transfers
3 Transfers
4 Transfers
T
Preliminary Datasheet
a
) cycle, bits 2-31 contain a
T
a
cycle. External bus
T
a
cycle, specifies the
d
)