FW80960VH100 Intel, FW80960VH100 Datasheet - Page 10

• Manufacturer Part Number: FW80960VH100
• Description: IC MPU I960VH 3V 100MHZ 324-BGA
• Manufacturer: Intel

Specifications of FW80960VH100

• Rohs Status: RoHS non-compliant
• Processor Type: i960
• Features: VH suffix, 32-Bit, 16K Cache
• Speed: 100MHz
• Voltage: 3V
• Mounting Type: Surface Mount
• Package / Case: 324-BGA
• Other names: 820682

80960VH
2.2
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Figure 2. 80960JT Core Block Diagram
i960
The processing power of the 80960VH comes from the 80960JT processor core. The 80960JT is a
new, scalar implementation of the 80960 Core Architecture.
80960JT Core processor.
Factors that contribute to the 80960 family core’s performance include:
The 80960 core operates out of its own 32-bit address space, which is independent of the PCI
address space. The local bus memory can be:
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P_CLK
Single-clock execution of most instructions
Independent Multiply/Divide Unit
Efficient instruction pipeline minimizes pipeline break latency
Register and resource scoreboarding allow overlapped instruction execution
128-bit register bus speeds local register caching
16 Kbyte two-way set-associative, integrated instruction cache
4 Kbyte direct-mapped, integrated data cache
1 Kbyte integrated data RAM delivers zero wait state program data
Made visible to the PCI address space
Kept private to the 80960 core
Allocated as a combination of the two
TAP
SRC1
5
®
Local Register
Global / Local
Register File
Core Features (80960JT)
Cache
8-Set
SRC2
Boundary Scan
PLL, Clocks,
Power Mgmt
128
Controller
3 Independent 32-Bit SRC1, SRC2, and DST Buses
DST
Multiply
Divide
Unit
Instruction Cache
16 Kbyte Two-Way Set
Instruction Sequencer
Generation
Execution
Address
Constants
Effective
Address
Unit
and
Control
Interface
Memory
32-bit Addr
32-bit Data
Unit
Figure •
address / data
32-bit buses
shows a block diagram of the
Preliminary Datasheet
Interrupt Controller
Memory-Mapped
Register Interface
4 Kbyte
Direct Mapped
Data Cache
Physical Region
Programmable
Bus Request
Configuration
Two 32-Bit
Control Unit
Data RAM
Queues
1 K byte
Timers
Bus
Data Bus
Control
Address/
Interrupt
Port
32
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