PCX755BVZFU300LE Atmel, PCX755BVZFU300LE Datasheet - Page 33

• Manufacturer Part Number: PCX755BVZFU300LE
• Description: IC MPU 32BIT 300MHZ 360PBGA
• Manufacturer: Atmel

Specifications of PCX755BVZFU300LE

• Processor Type: PowerPC 32-Bit RISC
• Speed: 300MHz
• Voltage: 2V
• Mounting Type: Surface Mount
• Package / Case: 360-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Table 8-7.
Notes:
2138G–HIREL–05/06
Parameter
Input Setup Times:
- Boundary
- TMS, TDI
Input Hold Times:
- Boundary
- TMS, TDI
Valid Times:
- Boundary
- TDO
Output Hold Times:
- Boundary
- TDO
TCK to output high impedance:
- Boundary
- TDO
1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal in ques-
2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
3. Non
4. Non
5. Guaranteed by design and characterization.
-
-
-
-
-
tion. The output timings are measured at the pins. All output timings assume a purely resistive 50Ω load (See
Time
scan data
scan data
scan data
scan data
scan data
(4)
JTAG AC Timing Specifications (Independent of SYSCLK)
-
-
-
JTAG signal input timing with respect to TCK.
JTAG signal output timing with respect to TCK.
of
(3)
-
(3)
(4)
flight delays must be added for trace lengths, vias, and connectors in the system.
Figure 8-9
Figure 8-9.
Figure 8-10
Figure 8-10. JTAG Clock Input Timing Diagram
(4)(5)
TCLK
provides the AC test load for TDO and the boundary-scan outputs of the PC755.
provides the JTAG clock input timing diagram.
Alternate AC Test Load for the JTAG Interface
Output
VM
t
JHJL
t
TCLK
VM = Midpoint Voltage (OV DD /2)
VM
Z 0 = 50Ω
VM
Symbol
t
(1)
t
t
t
t
t
t
t
t
t
DVJH
DXJH
JLOV
JLOV
JLOZ
JLDV
JLDV
JLDZ
IVJH
IXJH
(Continued)
R
t
JR
L
Min
15
12
25
12
= 50Ω
4
0
3
3
-
-
OV DD /2
Max
19
PC755/745
4
4
9
-
-
-
-
-
-
Figure
t
JF
Unit
ns
ns
ns
ns
ns
8-9).
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