PCX755BVZFU300LE Atmel, PCX755BVZFU300LE Datasheet - Page 29

• Manufacturer Part Number: PCX755BVZFU300LE
• Description: IC MPU 32BIT 300MHZ 360PBGA
• Manufacturer: Atmel

Specifications of PCX755BVZFU300LE

• Processor Type: PowerPC 32-Bit RISC
• Speed: 300MHz
• Voltage: 2V
• Mounting Type: Surface Mount
• Package / Case: 360-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Table 8-5.
Notes:
2138G–HIREL–05/06
Parameter
L2CLK frequency
L2CLK cycle time
L2CLK duty cycle
Internal DLL
DLL capture window
L2CLKOUT output
L2CLKOUT output jitter
1. L2CLK outputs are L2CLK_OUTA, L2CLK_OUTB, L2CLK_OUT and L2SYNC_OUT pins. The L2CLK frequency to core fre-
2. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage.
3. The DLL re
4. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 110 MHz. This adds more delay to each tap of the DLL.
5. Allowable skew between L2SYNC_OUT and L2SYNC_IN.
6. This output jitter number represents the maximum delay of one tap forward or one tap back from the current DLL tap as the
7. Guaranteed by design.
quency settings must be chosen so that the resulting L2CLK frequency and core frequency do not exceed their respective
maximum or minimum operating frequencies. The maximum L2LCK frequency will be system dependent. L2CLK_OUTA and
L2CLK_OUTB must have equal loading.
compute the actual time duration in nanoseconds. Re
phase comparator seeks to minimize the phase difference between L2SYNC_IN and the internal L2CLK. This number must
be comprehended in the L2 timing analysis. The input jitter on SYSCLK affects L2CLKOUT and the L2 address/data/control
signals equally and therefore is already comprehended in the AC timing and does not have to be considered in the L2 timing
analysis.
-
relock time
L2CLK Output AC Timing Specification. At
165 mV and OV
(1)(4)
(2)(7)
-
to
(5)(7)
-
output skew
-
lock time is specified in terms of L2CLKs. The number in the table must be multiplied by the period of L2CLK to
(6)(7)
(3)(7)
Functionality of core-to-L2 divisors of 1 or 1.5 is verified at less than maximum rated
frequencies.
L2 input and output signals are latched or enabled respectively by the internal L2CLK (which is
SYSCLK multiplied up to the core frequency and divided down to the L2CLK frequency). In other
words, the AC timings of
dent of L2SYNC_IN. In a closed loop system, where L2SYNC_IN is driven through the board
trace by L2SYNC_OUT, L2SYNC_IN only controls the output phase of L2CLKOUTA and
L2CLKOUTB which are used to latch or enable data at the SRAMs. However, since in a closed
loop system L2SYNC_IN is held in phase alignment with the internal L2CLK, the signals of
Table 8-6
nal L2CLK. During manufacturing test, these times are actually measured relative to SYSCLK.
The L2SYNC_OUT signal is intended to be routed halfway out to the SRAMs and then returned
to the L2SYNC_IN input of the PC755 to synchronize L2CLKOUT at the SRAM with the proces-
sor’s internal clock. L2CLKOUT at the SRAM can be offset forward or backward in time by
shortening or lengthening the routing of L2SYNC_OUT to L2SYNC_IN. See Freescale Applica-
tion Note AN179/D “PowerPC
The L2CLKOUTA and L2CLKOUTB signals should not have more than two loads.
DD
(6)(7)
= 1.8V 100 mV and OV
and
Table 8-7
are referenced to this signal rather than the not-externally-visible inter-
Table 8-6 on page 31
™
DD
Symbols
f
t
t
–
–
t
–
CHCL
L2CSKW
L2CLK
L2CLK
Backside L2 Timing Analysis for the PCB Design Engineer.”
= 2.0V 100 mV
-
lock timing is guaranteed by design and characterization.
V
/t
DD
L2CLK
= A
V
DD
= 2.0V 100 mV; -55 ≤ T
and
Table 8-7 on page 32
Min
640
2.5
80
45
0
–
–
All Speed Grades
J
±150
Max
12.5
450
≤ +125
55
10
50
–
are entirely indepen-
PC755/745
°
C, OV
DD
L2CLK
= 3.3V
MHz
Unit
ns
ns
ps
ps
%
29