PCX755BVZFU300LE Atmel, PCX755BVZFU300LE Datasheet - Page 31

• Manufacturer Part Number: PCX755BVZFU300LE
• Description: IC MPU 32BIT 300MHZ 360PBGA
• Manufacturer: Atmel

Specifications of PCX755BVZFU300LE

• Processor Type: PowerPC 32-Bit RISC
• Speed: 300MHz
• Voltage: 2V
• Mounting Type: Surface Mount
• Package / Case: 360-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

8.2.1.3
Table 8-6.
Notes:
2138G–HIREL–05/06
Parameter
L2SYNC_IN rise and Fall Time
Setup Times: Data and Parity
Input Hold Times: Data and Parity
Valid Times:
All Outputs when L2CR[14-15] = 00
All Outputs when L2CR[14-15] = 01
All Outputs when L2CR[14-15] = 10
All Outputs when L2CR[14-15] = 11
Output Hold Times:
All Outputs when L2CR[14-15] = 00
All Outputs when L2CR[14-15] = 01
All Outputs when L2CR[14-15] = 10
All Outputs when L2CR[14-15] = 11
L2SYNC_IN to High Impedance:
All Outputs when L2CR[14-15] = 00
All Outputs when L2CR[14-15] = 01
All Outputs when L2CR[14-15] = 10
All Outputs when L2CR[14-15] = 11
1. Rise and fall times for the L2SYNC_IN input are measured from 20% to 80% of L2OV
2. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of
3. All output specifications are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the midpoint of the sig-
4. The outputs are valid for both single-ended and differential L2CLK modes. For pipelined registered synchronous Bur-
5. Guaranteed by design and characterization.
6. Revisions prior to Rev 2.8 (Rev E) were limited in performance.and did not conform to this specification. Contact your local
the input L2SYNC_IN (see
nal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50Ω load (See
Figure 8-1 on page
stRAMs, L2CR[14
recommended.
Atmel sales office for more information.
(3)(4)
L2 Bus Input AC Specifications
L2 Bus Interface AC Timing Specifications at Recommended Operating Conditions
(3)
Table 8-6
ure 8-6 on page 32
on page
-
(2)
15] = 01 or 10 is recommended. For pipelined late write synchronous BurstRAMs, L2CR[14
(1)
25).
(3)(5)
(2)
32.
Figure 6-3 on page
provides the L2 bus interface AC timing specifications for the PC755 as defined in
and
Figure 8-7 on page 32
20). Input timings are measured at the pins.
t
L2CR
Symbol
t
t
t
t
t
DVL2CH
DXL2CH
L2CHOV
L2CHOX
L2CHOZ
& t
L2CF
for the loading conditions described in
Min
1.2
0.5
0.7
0.9
1.1
–
0
-
-
-
-
-
-
-
-
All Speed Grades
DD
.
Max
1.0
3.1
3.2
3.3
3.7
2.4
2.6
2.8
3.0
-
-
-
-
-
-
PC755/745
-
15] = 11 is
Unit
Figure 8-8
ns
ns
ns
ns
ns
ns
Fig-
31