PCX755BVZFU300LE Atmel, PCX755BVZFU300LE Datasheet - Page 28

• Manufacturer Part Number: PCX755BVZFU300LE
• Description: IC MPU 32BIT 300MHZ 360PBGA
• Manufacturer: Atmel

Specifications of PCX755BVZFU300LE

• Processor Type: PowerPC 32-Bit RISC
• Speed: 300MHz
• Voltage: 2V
• Mounting Type: Surface Mount
• Package / Case: 360-PBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Figure 8-4
Figure 8-4.
8.2.1.2
28
PC755/745
provides the input/output timing diagram for the PC755.
(Except TS, ABB,
L2 Clock AC Specifications
TS, ABB, DBB
Input/Output Timing Diagram
ARTRY, DBB)
All Outputs
All Inputs
SYSCLK
AR
TRY
The L2CLK frequency is programmed by the L2 Configuration Register (L2CR[4:6]) core-to-L2
divisor ratio. See
Table 8-5
Figure 8-5 on page
The minimum L2CLK frequency of
DLL. The variable-tap DLL introduces up to a full clock period delay in the L2CLKOUTA,
L2CLKOUTB, and L2SYNC_OUT signals so that the returning L2SYNC_IN signal is phase
aligned with the next core clock (divided by the L2 divisor ratio). Do not choose a core-to-L2 divi-
sor which results in an L2 frequency below this minimum, or the L2CLKOUT signals provided for
SRAM clocking will not be phase aligned with the PC755 core clock at the SRAMs.
The maximum L2CLK frequency shown in
few L2 SRAM designs will be able to operate in this mode. Most designs will select a greater
core-to-L2 divisor to provide a longer L2CLK period for read and write access to the L2 SRAMs.
The maximum L2CLK frequency for any application of the PC755 will be a function of the AC
timings of the PC755, the AC timings for the SRAM, bus loading, and printed circuit board trace
length.
Freescale is similarly limited by system constraints and cannot perform tests of the L2 interface
on a socketed part on a functional tester at the maximum frequencies of
functional operation and AC timing information are tested at core-to-L2 divisors of 2 or greater.
provides the potential range of L2CLK output AC timing specifications as defined in
VM
Table 8-5 on page 29
30.
t IVKH
t KHOE
t KHOV
t KHOV
VM = Midpoint Voltage (OV
t KHOV
Table 8-5
VM
for example core and L2 frequencies at various divisors.
Table 8-5
t KHOX
t KHOX
t IXKH
is specified by the maximum delay of the internal
t KHABPZ
t KHARP
t KHOX
DD
/2 or V
is the core frequency divided by one. Very
IN
/2)
VM
t KHARPZ
t KHOZ
t KHOV
t KHOZ
Table
2138G–HIREL–05/06
8-5. Therefore