MC68030RC50C Freescale Semiconductor, MC68030RC50C Datasheet - Page 434

• Manufacturer Part Number: MC68030RC50C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC50C

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

MOTOROLA
the MC68030 writes to user data space at the previously calculated program
transfer as required. The operand parts are stored in memory using ascending
from the preceding primitive. That is, this primitive uses the value from an
fer data, or transfer multiple coprocessor registers primitive without modi-
take address and transfer data primitive is not available to the write to pre-
viously evaluated effective address primitive.
that can be interrupted, and the bus can be arbitrated between the cycles.
does not check the type of effective address used with this primitive. For
example, if the previously evaluated effective address was program counter
Operands longer than four bytes are transferred in increments of four bytes
(operand parts) when possible. The main processor reads a long-word op-
erand part from the operand CIR and transfers this part to the current effective
address. The transfers continue in this manner using ascending memory
addresses beginning with the address in the MC68030 temporary register.
The execution of this primitive does not modify any of the registers in the
address mode is the predecrement or postincrement mode. If the previously
evaluated effective addressing mode used any of the MC68030 internal ad-
dress or data registers, the effective address value used is the final value
evaluate and transfer effective address, evaluate effective address and trans-
fication.
The take address and transfer data primitive described in the next section
does not replace the effective address value that has been calculated by the
A coprocessor can issue an evaluate effective address and transfer data
that is not indivisible. The bus cycles for this operation are normal bus cycles
request writes to only alterable effective addressing modes, the MC68030
relative and the MC68030 is atthe user privilege level (S=0 in status register),
relative address (the 32-bit value in the temporary internal register of the
processor).
locations until all of the long-word operand parts are transferred, and any
remaining operand part is then transferred using a one-, two-, or three-byte
MC68030 programmer's model, even if the previously evaluated effective
MC68030. The address that the main processor obtains in response to the
primitive followed by this primitive to perform a read-modify-write operation
MC68030 USER'S MANUAL
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