MC68030RC50C Freescale Semiconductor, MC68030RC50C Datasheet - Page 162

• Manufacturer Part Number: MC68030RC50C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC50C

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

7.1 B U S T R A N S F E R S I G N A L S
MOTOROLA
SECTION 7
The MC68030 architecture supports byte, word, and long-word operands,
The MC68030 allows byte, word, and long-word operands to be located in
The bus transfers information between the MC68030 and an external mem-
This section provides a functional description of the bus, the signals that
control it, and the bus cycles provided for data transfer operations, It also
ation. Operation of the bus is the same whether the processor or an external
the point of view of the bus master. For exact timing specifications, refer to
SECTION 13 ELECTRICAL CHARACTERISTICS.
allowing access to 8-, 16-, and 32-bit data ports through the use of asyn-
chronous cycles controlled by the data transfer and size acknowledge inputs
Synchronous bus cycles controlled by the synchronous termination signal
operand transfer due to either misalignment or a port width smaller than the
operand size. Instruction words and their associated extension words must
of word or long-word operands can cause the MC68030 to perform multiple
optimized if word and long-word memory operands are aligned on word or
ory, coprocessor, or peripheral device. External devices can accept or provide
described in this section. The maximum number of bits accepted or provided
during a bus transfer is defined as the port width. The MC68030 contains an
BUS OPERATION
describes the error and halt conditions, bus arbitration, and the reset oper-
device is the bus master; the names and descriptions of bus cycles are from
(DSACK0 and DSACK1).
(STERM) can only be used to transfer data to and from 32-bit ports.
memory on any byte boundary. For a misaligned transfer, more than one
bus cycle may be required to complete the transfer, regardless of port size.
For a port less than 32 bits wide, multiple bus cycles may be required for an
be aligned on word boundaries. The user should be aware that misalignment
bus cycles for the operand transfer; therefore, processor performance is
long:word boundaries, respectively.
8 bits, 16 bits, or 32 bits in parallel and must follow the handshake protocol
MC68030 USER'S MANUAL
7-1
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7