MC68030RC50C Freescale Semiconductor, MC68030RC50C Datasheet - Page 292

• Manufacturer Part Number: MC68030RC50C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC50C

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

MOTOROLA
the status register with the value read from the stack, and then begins RTE
When the processor executes an RTE instruction, it examines the stack frame
what type of context restoration it requires. This section describes the pro-
cessing for each of the stack frame types; refer to 8.3 COPROCESSOR CON-
SIDERATIONS for a description of the stack frame type formats.
value from the frame, increments the active stack pointer by eight, updates
word from the stack frame on top of the active stack (which may or may not
operations corresponding to that format. In most cases, the throwaway frame
stack, the S and M bits are set. In that case, there is a normal four-word frame
or a ten-word coprocessor mid-instruction frame on the master stack. How-
the corresponding internal registers, and increments the stack pointer by 20.
The processor then reads from the response register of the coprocessor that
to
coprocessor-related exceptions.
the format value on the stack for validity. In addition, for the long stack frame,
the processor compares the version number in the stack with its own version
check is required in a multiprocessor system to ensure that the data is prop-
erly interpreted by the RTE instruction. The RTE instruction also reads from
on top of the active supervisor stack to determine if it is a valid frame and
For a normal four-word frame, the processor updates the status register and
program counter with the data read from the stack, increments the stack
pointer by eight, and resumes normal instruction execution.
For the throwaway four-word stack, the processor reads the status register
processing again, as shown in Figure 8-8. The processor reads a new format
be the same stack used for the previous operation) and performs the proper
is on the interrupt stack and when the status register value is read from the
ever, the second frame may be any format (even another throwaway frame)
and may reside on any of the three system stacks.
For the six-word stack frame, the processor restores the status register and
program counter values from the stack, increments the active supervisor
stack pointer by 12, and resumes normal instruction execution.
For the coprocessor mid-instruction stack frame, the processor reads the
status register, program counter, instruction address, internal register values,
and the evaluated effective address from the stack, restores these values to
initiated the exception to determine the next operation to be performed. Refer
For both the short and long bus fault stack frames, the processor first checks
number. The version number is located in the most significant nibble (bits
15-12) of the word at location SP+$36 in the long stack frame. This validity
SECTION 10 COPROCESSOR INTERFACE DESCRIPTION
MC68030 USER'S MANUAL
for details of
8-25
8