MC68030RC50C Freescale Semiconductor, MC68030RC50C Datasheet - Page 258

• Manufacturer Part Number: MC68030RC50C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC50C

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

MOTOROLA
technique allows processing of bus requests during data transfer cycles.
The timing diagram shows that BR is negated at the time that BGACK is
signal. When the requesting device receives BG and more than one external
device can be bus master, the requesting device should begin whatever
for which it is bus master. The following conditions must be met for an
Figure 7-59 is a flowchart showing the detail involved in bus arbitration for
a single device. Figure 7-60 is a timing diagram for the same operation. This
asserted. This type of operation applies to a system consisting of the pro-
cessor and one device capable of bus mastership. In a system having a
number of devices capable of bus mastership, the bus request line from each
device can be wire-ORed to the processor. In such a system, more than one
The timing diagram in Figure 7-60 shows that BG is negated a few clock
cycles after the transition of the BGACK signal. However, if bus requests are
still pending after the negation of BG, the processor asserts another BG within
a few clock cycles after it was negated. This additional assertion of BG allows
external arbitration circuitry to select the next bus master before the current
additional information about the three steps in the arbitration process.
a double bus fault.
arbitration is required. The external device asserts BGACK when it assumes
bus mastership and maintains BGACK during the entire bus cycle (or cycles)
external device to assume mastership of the bus through the normal bus
arbitration procedure:
bus request can be asserted simultaneously.
bus master has finished with the bus. The following paragraphs provide
Bus arbitration requests are recognized during normal processing, RESET
assertion, HALT assertion, and even when the processor has halted due to
• The termination signal (DSACKx or STERM) for the most recent cycle
• BGACK must be inactive, indicating that no other bus master has claimed
• It must have received BG through the arbitration process.
• AS must be negated, indicating that no bus cycle is in progress, and the
ownership of the bus,
must have become inactive, indicating that external devices are off the
bus (optional, refer to 7.7.3 Bus Grant Acknowledge).
external device must ensure that all appropriate processor signals have
been placed in the high-impedance state (by observing specification #7
in MC68030EC/D,
MC68030 Electrical Specifications).
MC68030 USER'S MANUAL
7-97
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