MC68030FE33C Freescale Semiconductor, MC68030FE33C Datasheet - Page 562

• Manufacturer Part Number: MC68030FE33C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

MOTOROLA
the status register do not result in a refill request. However, operations like
the MOVE <ea>,SR instruction, which updates the status register, cause a
function codes. When the program space changes, the processor must fetch
An instruction like the PMOVE <ea>,TC, which changes the translation con-
trol register, requires the processor to fetch data from the new address trans-
causes two refill requests when the condition being tested is false. To opti-
condition is tested. If the condition is false, another refill is requested to
continue with the next sequential instruction.
struction boundaries as identified by the STATUS signal. STATUS asserting
for one clock cycle identifies normal instruction boundaries. Note that the
assertion of REFILL does not necessarily correspond to the assertion of
STATUS. Both STATUS and REFILL assert and negate from the falling edge
of the CLK signal.
tifies a trace or interrupt exception. Instruction boundary information is still
fetched, the REFILL signal asserts (not shown) to identify a change in program
flow.
structions that modify the program counter flow, and status register manip-
ulations. Logical and arithmetic operations affecting the condition codes of
refill request since this can change the program space as defined by the
data from the new space to replace data already prefetched from the old
program space. Similarly, operations which affect the address translation
mechanism of the memory management unit (MMU) cause a refill request.
lation base. The Test Condition, Decrement, and Branch (DBcc) instruction
mize branching performance, the DBcc instruction requests a refill before the
Figure 12-19 illustrates the relation between the CLK signal and normal in-
interrupt exception boundary. STATUS asserting for two clock cycles iden-
present since both trace and interrupt exceptions are processed only at in-
struction boundaries. Before the exception handler instructions are pre-
Figure 12-20 shows a normal instruction boundary followed by a trace or
I N STRUCTI O N
80UNDARI E S
STATUS
R EFI L ' ~ ' C
CLK
J
Figure 12-19. Normal Instruction Boundaries
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MC68030 USER'S MANUAL
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