MC68030FE33C Freescale Semiconductor, MC68030FE33C Datasheet - Page 203

• Manufacturer Part Number: MC68030FE33C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

7
7-42
State 4
State 5
State 2
State 3
State
the data bus. As long as at least one of the DSACKx signals is recognized
the cycle terminates one clock later. If DSACKx is not recognized by the
times around the end of $2. If wait states are added, the processor con-
tinues to sample the DSACKx signals on the falling edges of the clock until
to latch data from the appropriate byte(s) of the data bus (D24-D31, D16-D23,
The processor issues no new control signals during $4.
The processor asserts DS during $3, indicating that the data is stable on
start of $3, the processor inserts wait states instead of proceeding to $4
and $5. To ensure that wait states are inserted, both DSACK0 and DSACK1
one is recognized. The selected device uses
The processor negates AS and DS during $5. It holds the address and data
valid during $5 to provide address hold time for memory systems. R/W,
SIZ0-SIZ1, FC0-FC2, and DBEN also remain valid throughout $5.
The external device must keep DSACKx asserted until it detects the ne-
gation of AS or DS (whichever it detects first). The device must negate
One-half clock later in $1, the processor asserts AS, indicating that the
address on the address bus is valid. The processor also asserts DBEN
during $1, which can enable external data buffers. In addition, the ECS
During $2, the processor places the data to be written onto the D0-D31,
and samples DSACKx at the end of $2.
by the end of $2 (meeting the asynchronous input setup time requirement),
must remain negated throughout the asynchronous input setup and hold
D8-D15, and D0-D7). SIZ0-SIZi and A0-A1 select the bytes of the data
bus. If it has not already done so, the device asserts DSACKx to signal that
it has successfully stored the data.
DSACKx within approximately one clock period after sensing the negation
of AS or DS. DSACKx signals that remain asserted beyond this limit may
be prematurely detected for the next bus cycle.
(and OCS, if asserted) signal is negated during $1.
1
MC68030 USER'S MANUAL
R/W,
DS, SIZ0-SIZ1, and A0-A1
MOTOROLA