MC68030FE33C Freescale Semiconductor, MC68030FE33C Datasheet - Page 555

• Manufacturer Part Number: MC68030FE33C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

21
12.6 E X T E R N A L
12-30
validation.
The MC68030 late BERR/HALT facility allows an external device to signal
trying that cycle if an error condition is detected. Since one critical access
to terminate a bus cycle before data is valid on the processor data bus. If the
The critical path for the 3-1-1-1 memory bank is not the first long-word access
2-1-1-1 burst cycle. However, for 3-1-1-1 burst cycles, the designer might
consider memory banks which are 64 or 128 bits wide. In this manner, the
access time for the subsequent long words can be hidden underneath the
access of the previous long word(s).
To provide lower average access times to memory, some systems implement
caches local to the main processor that store recently used instructions and/
or data. For the MC68030, several architectural options are available to the
cache designer. The primary decisions are whether to configure the cache
as an asynchronous or synchronous device and whether the cache accesses
are terminated early (before the cache lookup is complete) or only after
completion of a bus cycle by asserting DSACKx or STERM and later (ap-
data validation fails, the memory controller can then abort (BERR) or retry
schemes where the cycle can be terminated as soon as data becomes avail-
the validation is completed before late abort or retry must be indicated.
The major consideration in choosing whether or not to utilize late retry for
a data operand crosses a long-word boundary. Another enhancement might
be to alter the TERM control circuitry with the addition of a write latch mech-
anism to run two-clock writes.
as in the 2-1-1-1 memory bank, but rather the subsequent long words during
burst cycles. No alternative architecture can correct the critical path for the
proximately one clock period or one-half clock, respectively) aborting or re-
path in many memory structures is the assertion of DSACKx/STERM to avoid
additional wait states, the late abort capability allows the memory controller
(BERR/HALT) the cycle. This technique is useful in memory error detection
able and the error checking can occur during the period between the signaling
of termination of the cycle and the latching of data by the processor with a
can be used in cache implementations in which the cache tag validation
cannot be completed before termination of the cycle must be signaled but
an external cache miss is the overhead involved in retrying a bus cycle after
a miss in the cache. The minimum penalty is the four clock periods required
late retry or abort signaled upon error indication. Likewise, this technique
C A C H E S
MC68030 USER'S MANUAL
MOTOROLA