MC68030FE33C Freescale Semiconductor, MC68030FE33C Datasheet - Page 250

• Manufacturer Part Number: MC68030FE33C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

7.5.2 Retry O p e r a t i o n
MOTOROLA
The processor retries any read or write cycle of a read-modify-write operation
write operation, except during the first read cycle. Any device that requires
take the appropriate action to resolve this type of fault when it occurs.
When the BERR and HAL-i" signals are both asserted by an external device
similar to the delayed bus error signal described previously, can also occur,
The processor terminates the bus cycle, places the control signals in their
the previous cycle using the same access information (address, function code,
size, etc.) The BERR signal should be negated before $2 of the read cycle to
ensure correct operation of the retried cycle. Figure 7-54 shows a retry op-
eration of an asynchronous cycle, and Figure 7-55 shows a retry operation
of a synchronous cycle.
separately; RMC remains asserted during the entire retry sequence.
of BERR and HALT) causes the processor to retry the bus cycle and assert
does not cause a retry operation, even if the requested operand is misaligned.
Assertion of BERR and HALT during a subsequent cycle of a burst operation
causes independent BERR and HALT operations. The external bus activity
described for the bus error during a burst operation.
Asserting BR along with BERR and HALT provides a relinquish and retry
operation. The MC68030 does not relinquish the bus during a read-modify-
the processor to give up the bus and retry a bus cycle during a read-modify-
write cycle must either assert BERR and BR only (HALT must not be included)
or use the single wire arbitration method discussed in 7.7.4 Bus Arbitration
Control. The bus error handler software should examine the read-modify-
write bit in the special status word (refer to 8.2.1 Special Status Word) and
during a bus cycle, the processor enters the retry sequence. A delayed retry,
both for synchronous and asynchronous cycles.
inactive state, and does not begin another bus cycle until the HALT signal is
negated by external logic. After a synchronization delay, the processor retries
On the initial access of a burst operation, a retry (indicated by the assertion
CBREQ again. Figure 7-56 shows a late retry operation that causes an initial
burst operation to be repeated. However, signaling a retry with simultaneous
BERR and HALT during the second, third, or fourth cycle of a burst operation
remains halted until HALT is negated and the processor acts as previously
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MC68030 USER'S MANUAL
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