MC68030FE33C Freescale Semiconductor, MC68030FE33C Datasheet - Page 123

• Manufacturer Part Number: MC68030FE33C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

4
4.3.1 Exception Vectors
4-6
4.3 EXCEPTION PROCESSING
An exception is defined as a special condition that pre-empts normal pro-
tracing, and breakpoints are internal conditions that cause exceptions. The
TRAP, TRAPcc, TRAPV, cpTRAPcc, CHK, CHK2, RTE, and DIV instructions can
The vector base register (VBR) contains the base address of the 1024-byte
vectors contain the memory addresses of routines that begin execution at
the completion of exception processing. These routines perform a series of
operations appropriate for the corresponding exceptions. Because the ex-
The address of an exception vector is derived from an 8-bit vector number
cessing. Both internal and external conditions cause exceptions. External
conditions that cause exceptions are interrupts from external devices, bus
errors, coprocessor detected errors, and reset. Instructions, address errors,
all generate exceptions as part of their normal execution. In addition, illegal
instructions, privilege violations, and coprocessor protocol violations cause
exceptions.
a program
the exception vector table and an exception stack frame. The following par-
CESSING.
TION 10 COPROCESSOR INTERFACE DESCRIPTION.
exception vector table, which consists of 256 exception vectors. Exception
ception vectors contain memory addresses, each consists of one long word,
except for the reset vector. The reset vector consists of two long words: the
address used to initialize the interrupt stack pointer and the address used to
and the VBR. The vector numbers for some exceptions are obtained from an
external device; others are supplied automatically by the processor. The
which it adds to the VBR. The sum is the memory address of the vector. All
exception vectors are located in supervisor data space, except the reset vec-
tor, which is located in supervisor program space. Only the initial reset vector
vector table, the
Exception processing, which is the transition from the normal processing of
agraphs describe the vector table and a generalized exception stack frame.
Exception processing is discussed in detail in SECTION 8
initialize the program counter.
processor multiplies the vector number by four to calculate the vector offset,
is fixed in the processor's memory map; once initialization is complete, there
are no fixed assignments. Since the VBR provides the base address of the
Coprocessor detected exceptions are discussed in detail in
to the processing required for the exception condition, involves
vector
MC68030 USER'S MANUAL
table
can
be located
anywhere
in memory; it can
EXCEPTION PRO-
MOTOROLA
SEC-