MC68030FE33C Freescale Semiconductor, MC68030FE33C Datasheet - Page 207

• Manufacturer Part Number: MC68030FE33C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

7
7-46
State 5
State 2
State 3
State 4
Idle States
the selected device may assert the DSACKx signals.
As long as at least one of the DSACKx signals is recognized by the end of
the processor continues to sample the DSACKx signals on the falling edges
The processor samples the level of CIIN at the beginning of $4. At the end
of $4, the processor latches the incoming data.
The processor negates AS, DS, and DBEN during $5. If more than one read
cycle is required to read in the operand(s), S0-$5 are repeated for each
The external device keeps its data and DSACKx signals asserted until it
The processor does not assert any new control signals during the idle
time. $6-$11 are omitted if no write cycle is required. If a write cycle is
data buffers. The selected device uses R/W, SIZ0-SIZ1, A0-A1, and DS to
$2 (meeting the
on the next falling edge of the clock, and the cycle terminates. If DSACKx
is not recognized by the start of $3, the processor inserts wait states instead
of proceeding to $4 and $5. To ensure that wait states are inserted, both
DSACK0 and DSACK1 must remain negated throughout the asynchronous
input setup and hold times around the end of $2. If wait states are added,
of the clock until one is recognized.
read cycle. When finished reading, the processor holds the address, R/W,
and FC0-FC2 valid in preparation for the write portion of the cycle.
detects the negation of AS or DS (whichever it detects first). The device
must remove the data and negate DSACKx within approximately one clock
period after sensing the negation of AS or DS. DSACKx signals that remain
asserted beyond this limit may be prematu rely detected for the next portion
of the operation.
states, but it may internally begin the modify portion of the cycle at this
conflicts with the preceding read portion of the cycle; the data bus is not
driven until $8.
During state 2 ($2), the processor drives DBEN active to enable external
place information on the data bus. Any or all of the bytes (D24-D31, D16-D23,
D8-D15, and D0-D7) are selected by SIZ0-SIZ1 and A0-AI. Concurrently,
required, the R/W signal remains in the read mode until $6 to prevent bus
asynchronous
MC68030 USER'S MANUAL
input setup time requirement), data is latched
MOTOROLA