MC68030FE33C Freescale Semiconductor, MC68030FE33C Datasheet - Page 262

• Manufacturer Part Number: MC68030FE33C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

MOTOROLA
when bus mastership is returned to the MC68030.
the arbiter changes to the center state, state 3, and negates grant G. The next
State changes occur on the next rising edge of the clock after the internal
signal is valid. The BG signal transitions on the falling edge of the clock after
a state is reached during which G changes. The bus control signals (controlled
by T) are driven by the processor, immediately following a state change,
State 0, at the top center of the diagram, in which G and T are both negated,
and acknowledge A keep the arbiter in state 0 as long as they are both
clock takes the arbiter to state 4, at the upper right, in which grant G remains
is the state of the bus arbiter while the processor is bus master. Request R
negated. When a request R is received, both grant G and signal T are asserted
(in state 1 at the top left). The next clock causes a change to state 2, at the
lower left, in which G and T are held, The bus arbiter remains in that state
until acknowledge A is asserted or request R is negated. Once either occurs,
Figure 7-61. Bus Arbitration State Diagram
A - BUS GRANTACKNOWLEDGE
G • BUS GRANT
T . THREE-STATE CONTROL TO BUS CONTROL LOGIC
X • DON'T CARE
R • BUS REQUEST
NOTE: T h e B-G o u t p u t w i l l not be a s s e r t e d w h i l e R M C is a s s e r t e d .
MC68030 USER'S MANUAL
RA
7=101
7