MC68360CAI25L Freescale Semiconductor, MC68360CAI25L Datasheet - Page 509

• Manufacturer Part Number: MC68360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• Supply Voltage Range: 3V To 3.6V, 4.75V To 5.25V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

The HDLC event register is a memory-mapped register that may be read at any time. A bit
is cleared by writing a one (writing a zero does not affect a bit’s value). More than one bit
may be cleared at a time. All unmasked bits must be cleared before the CP will clear the
internal interrupt request. This register is cleared at reset.
Bits 15–13, 6, 5—Reserved
GLr—Glitch on Rx
RXD
CD
HDLC SCCE
NOTES:
HDLC SCCE
TXD
RTS
CTS
NOTES:
15
These bits should be written with zeros.
A clock glitch was detected by this SCC on the receive clock.
1. RXB event assumes receive buffers are 6 bytes each.
2. The second IDL event occurs after 15 ones are received in a row.
3. The FLG interrupts show the beginning and end of flag reception.
4. The FLG interrupt at the end of the frame may precede the RXF interrupt due to receive FIFO latency.
5. The CD event must be programmed in the port C parallel I/O, not in the SCC itself.
6. F = flag, A = address byte, C = control byte, I = information byte, and CR = CRC byte.
EVENTS
1. TXB event shown assumes all three bytes were put into a single buffer.
2. Example shows one additional opening flag. This is programmable.
3. The CTS event must be programmed in the port C parallel I/O, not in the SCC itself.
EVENTS
TRANSMITTED BY HDLC
RECEIVED IN HDLC
14
—
TIME
FRAME
FRAME
13
LINE IDLE
CD
GLr
12
LINE IDLE
Figure 7-53. HDLC Interrupt Event Example
IDL
Freescale Semiconductor, Inc.
GLt
11
F
For More Information On This Product,
FLG
F
DCC
A
10
FLG
CTS
MC68360 USER’S MANUAL
A
STORED IN RX BUFFER
Go to: www.freescale.com
F
FLG
C
9
F
I
STORED IN
TX BUFFER
A
IDL
I
8
A
I
RXB
C CR CR
GRA
CR CR
7
F
Serial Communication Controllers (SCCs)
RXF
FLG
6
F
TXB
—
FLG
5
IDL
TXE
LINE IDLE
CTS
4
LINE IDLE
CD
RXF
3
BSY
2
TXB
1
RXB
0