MC68360CAI25L Freescale Semiconductor, MC68360CAI25L Datasheet - Page 223

• Manufacturer Part Number: MC68360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• Supply Voltage Range: 3V To 3.6V, 4.75V To 5.25V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

When IPIPE1 is low during a clock cycle, it indicates the use of data from IRB on that clock
cycle. IPIPE1 should be sampled by the user on the falling edge of CLKO1. Regardless of
the presence of valid data in IRA or IRL, the contents of IRB are invalidated when IPIPE1 is
asserted. If IRA or IRL contain valid data, the data is copied into IRB (IRA/IRL
the IRB stage is revalidated.
When IPIPE0 is low during a clock cycle, it indicates the start of a new instruction and sub-
sequent replacement of data in IRC. This action causes a full advance of the pipeline (IRB
cycle.
Data loaded into IRA and IRL propagates automatically through subsequent empty pipeline
stages. Signals that show the progress of instructions through IRB and IRC are necessary
to accurately monitor pipeline operation. These signals are provided by IRA, IRL and IRB
validity bits. When a pipeline advance occurs, the validity bit of the stage being loaded is set,
and the validity bit of the stage supplying the data is negated.
Because instruction execution is not timed to bus activity, IPIPE1–IPIPE0 are synchronized
with the system clock and not the bus. Figure 5-29 illustrates the timing in relation to the sys-
tem clock.
IRC and IRA/IRL
CLKO1
IPIPE1
IPIPE0
INSTRUCTION
IRB
IRA/IRL
START
Figure 5-28. Functional Model of Instruction Pipeline
IRB
IRC
Figure 5-29. Instruction Pipeline Timing Diagram
IRB). IRA and/or IRL is refilled during the next instruction fetch bus
Freescale Semiconductor, Inc.
(31–16)
DATA
For More Information On This Product,
BUS
(15–0)
DATA
BUS
IRA/IRL
LONG WORD
IRB
EXTENSION
MC68360 USER’S MANUAL
USED
Go to: www.freescale.com
IRA/IRL
IRB
R
A
R
L
I
I
EXTENSION
WORDS
R
I
B
OPCODES
RESIDUAL
R
C
I
INSTRUCTION
IRB
IRA/IRL
START
IRB
IRC
IRB), and
CPU32+