MC68360CAI25L Freescale Semiconductor, MC68360CAI25L Datasheet - Page 124

IC MPU QUICC 25MHZ 240-FQFP

MC68360CAI25L

Manufacturer Part Number
MC68360CAI25L
Description
IC MPU QUICC 25MHZ 240-FQFP
Manufacturer
Freescale Semiconductor

Specifications of MC68360CAI25L

Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
240-FQFP
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Supply Voltage (max)
5.25V
Operating Supply Voltage (min)
4.75V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
240
Package Type
FQFP
Controller Family/series
68K
Core Size
32 Bit
Cpu Speed
25MHz
No. Of Timers
4
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
FQFP
Supply Voltage Range
3V To 3.6V, 4.75V To 5.25V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant

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Bus Operation
4.5.4 Double Bus Fault
A double bus fault results when a bus error or an address error occurs during the exception
processing sequence for any of the following:
For example, the QUICC attempts to stack several words containing information about the
state of the machine while processing a bus error exception. If a bus error exception occurs
during the stacking operation, the second error is considered a double bus fault. When a
double bus fault occurs, the QUICC halts and drives the HALT line low. Only a reset opera-
tion can restart a halted QUICC. However, bus arbitration can still occur (refer to 4.6 Bus
Arbitration). A second bus error or address error that occurs after exception processing has
4-48
1. A previous bus error
2. A previous address error
3. A reset
FC3–FC0
DSACKx
D31–D0
A31–A0
BGACK
CLKO1
HALT
R/W
DS
BR
BG
AS
S0
Freescale Semiconductor, Inc.
For More Information On This Product,
S2
READ
Figure 4-33. HALT Timing
MC68360 USER’S MANUAL
S4
Go to: www.freescale.com
WHILE THE PROCESSOR IS
(ARBITRATION PERMITTED
HALTED)
HALT
S0
S2
READ
S4
S0

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