MC68360CAI25L Freescale Semiconductor, MC68360CAI25L Datasheet - Page 175

• Manufacturer Part Number: MC68360CAI25L
• Description: IC MPU QUICC 25MHZ 240-FQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68360CAI25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 240-FQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 240
• Package Type: FQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: FQFP
• Supply Voltage Range: 3V To 3.6V, 4.75V To 5.25V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Rounding yields:
The second result is preferred. The following code sequence illustrates how addition of a
series of table interpolations can be performed without loss of precision in the intermediate
results:
5.3.4.5 TABLE EXAMPLE 5: SURFACE INTERPOLATIONS. The various forms of table
can be used to perform surface (3D) TBLs. However, since the calculation must be split into
a series of 2D TBLs, it is possible to lose precision in the intermediate results. The following
code sequence, incorporating both TBLS and TBLSN, eliminates this possibility.
Before execution of this code sequence, Dx must contain fraction and entry numbers for the
two TBL, and Dm must contain the fraction for surface interpolation. The ea fields in the
TBLSN instructions point to consecutive columns in a 3D table. The TBLS size parameter
must be word if the TBLSN size parameter is byte, and must be long word if TBLSN is word.
Increased size is necessary because a larger number of significant digits is needed to
accommodate the scaled fractional results of the 2D TBL.
5.3.5 Nested Subroutine Calls
The LINK instruction pushes an address onto the stack, saves the stack address at which
the address is stored, and reserves an area of the stack for use. Using this instruction in a
series of subroutine calls will generate a linked list of stack frames.
L0:
TBLSN.B
TBLSN.B
TBLSN.B
ADD.L
ADD.L
ASR.L
BCC.B
ADDQ.B
L1: . . .
L0:
MOVE.W
TBLSN.B
TBLSN.B
TBLS.W
ASR.L
BCC.B
ADDQ.B
L1: . . .
Dx, Dm
Dm, Dl
#8, Dl
L1
#1, Dl
Dx, Dl
Dx:Dl, Dm
#8, Dm
L1
#1, Dl
ea Dx
ea Dx
ea Dl
ea , Dx
ea Dl
Freescale Semiconductor, Inc.
For More Information On This Product,
Long addition avoids problems with carry
Move radix point
Fraction MSB in carry
MC68360 USER’S MANUAL
Copy entry number and fraction number
Surface interpolation, with round
Read just the result
No round necessary
Half round up
Go to: www.freescale.com
0010 0000 . 0111 0000
0011 1111 . 0111 0000
0000 0001 . 0111 0000
0110 0001 . 0101 0000
0110 0001 .
CPU32+