MC68360CVR25L Freescale Semiconductor, MC68360CVR25L Datasheet - Page 687
![IC MPU QUICC 25MHZ 357-PBGA](/photos/6/76/67680/mfg_mpc860_series_sml.jpg)
MC68360CVR25L
Manufacturer Part Number
MC68360CVR25L
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360CVR25L
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
MC68360CVR25L
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Part Number:
MC68360CVR25LR2
Manufacturer:
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Quantity:
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7.14.7 Port B Registers
Port B has four memory-mapped, read-write, 16-bit control registers.
7.14.7.1 PORT B OPEN-DRAIN REGISTER (PBODR). The PBODR is a 16-bit register
that indicates a normal or wired-OR configuration of the port pins. (Bits 17 and 16 of PBODR
do not exist.) PBODR is cleared at system reset.
OD15
15
Signal
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
OD14
14
OD13
The user may freely configure any of the previous functions to
be output onto two pins at once, although there is typically no ad-
vantage in doing this (except in the case of a large fanout, where
it is advantageous to share the load between two pins).
13
PBPAR = 0
PORT B10
PORT B11
PORT B12
PORT B13
PORT B14
PORT B15
PORT B16
PORT B17
PORT B0
PORT B1
PORT B2
PORT B3
PORT B4
PORT B5
PORT B6
PORT B7
PORT B8
PORT B9
OD12
12
Freescale Semiconductor, Inc.
OD11
11
For More Information On This Product,
Table 7-20. Port B Pin Assignment
OD10
PBDIR = 0
SYMSYN1
SYMSYN2
10
SMRXD1
SMRXD2
SMTXD1
SMTXD2
RRJCT1
RRJCT2
BRGO4
BRGO1
BRGO2
RSTR2
L1ST1
L1ST2
L1ST3
L1ST4
MC68360 USER’S MANUAL
Go to: www.freescale.com
—
—
OD9
9
PBPAR = 1
OD8
NOTE
8
Pin Function
t
OD7
7
RTS3/L1RQB
RTS4/L1RQA
PBDIR = 1
L1CLKOB
L1CLKOA
SPIMOSI
SPIMISO
RSTRT1
SPISEL
SPICLK
BRGO3
DREQ1
DONE1
DONE2
DREQ2
DACK1
DACK2
RTS1
RTS2
OD6
6
OD5
5
OD4
4
SPIMISO = SPIMOSI
SYMSYN2 = GND
Input to On-Chip
OD3
SMRXD2 = GND
SPICLK = GND
DONE1 = V
DREQ1 = GND
3
Peripherals
V
V
V
GND
OD2
Parallel I/O Ports
DD
DD
—
DD
—
—
—
—
—
—
—
2
DD
OD1
1
OD0
0
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