MC68360CVR25L Freescale Semiconductor, MC68360CVR25L Datasheet - Page 651

• Manufacturer Part Number: MC68360CVR25L
• Description: IC MPU QUICC 25MHZ 357-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68360CVR25L

• Processor Type: M683xx 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

R—Ready
Bits 14, 10, 8–2—Reserved
W—Wrap (Final BD in Table)
I—Interrupt
L—Last
CM—Continuous Mode
The following status bits are written by the SPI after it has finished transmitting the associ-
ated data buffer.
UN—Underrun
ME—Multi-Master Error
This bit is valid only when the SPI is configured as a master; it should be written as a zero
in slave mode.
The SPI encountered a transmitter underrun condition while transmitting the associated
data buffer. This error condition is valid only when the SPI is configured as a slave.
This buffer was closed because the SPISEL pin was asserted when the SPI was operating
as a master. This indicates a synchronization problem between multiple masters on the
SPI bus.
0 = The data buffer associated with this BD is not ready for transmission. The user is
1 = The data buffer, which has been prepared for transmission by the user, has not
0 = This is not the last BD in the Tx BD table.
1 = This is the last BD in the Tx BD table. After this buffer has been used, the CP will
0 = No interrupt is generated after this buffer has been serviced.
1 = The TXB or TXE bit in the event register is set when this buffer is serviced. TXB
0 = This buffer does not contain the last character of the message.
1 = This buffer contains the last character of the message.
0 = Normal operation.
1 = The R-bit is not cleared by the CP after this BD is closed, allowing the associated
free to manipulate this BD or its associated data buffer. The CP clears this bit after
the buffer has been transmitted or after an error condition is encountered.
been transmitted or is currently being transmitted. No fields of this BD may be writ-
ten by the user once this bit is set.
receive incoming data into the first BD in the table (the BD pointed to by TBASE).
The number of Tx BDs in this table is programmable, and is determined only by the
W-bit and the overall space constraints of the dual-port RAM.
and TXE can cause interrupts if they are enabled.
data buffer to be retransmitted automatically when the CP next accesses this BD.
Freescale Semiconductor, Inc.
For More Information On This Product,
MC68360 USER’S MANUAL
Go to: www.freescale.com
Serial Peripheral Interface (SPI)