MC68360CVR25L Freescale Semiconductor, MC68360CVR25L Datasheet - Page 118
MC68360CVR25L
Manufacturer Part Number
MC68360CVR25L
Description
IC MPU QUICC 25MHZ 357-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68EN360VR25L.pdf
(14 pages)
2.MC68EN360VR25L.pdf
(2 pages)
3.MC68360AI25L.pdf
(962 pages)
Specifications of MC68360CVR25L
Processor Type
M683xx 32-Bit
Speed
25MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
357-PBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
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Part Number:
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Manufacturer:
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Quantity:
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Bus Operation
EXAMPLE A: A system uses a bus monitor timer to terminate accesses to an unpopulated
address space. The timer asserts BERR after timeout (case 3).
EXAMPLE B: A system uses error detection and correction on RAM contents. The designer
may:
4.5.1 Bus Errors
BERR can be used to abort the bus cycle and the instruction being executed. BERR takes
precedence over DSACKx provided it meets the timing constraints described in Section 10
Electrical Characteristics. If BERR does not meet these constraints, it may cause unpredict-
4-42
1. Delay DSACKx until data is verified and assert BERR and HALT simultaneously to in-
2. Delay DSACKx until data is verified and assert BERR with or without DSACKx if data
3. Return DSACKx prior to data verification; if data is invalid, BERR is asserted on the
4. Return DSACKx prior to data verification; if data is invalid, assert BERR and HALT on
NOTES:
N —The number of current even bus state (e.g., S2, S4, etc.)
A —Signal is asserted in this bus state
NA —Signal is not asserted in this state
X —Don't care
S —Signal was asserted in previous state and remains asserted in this state
Case
Num
dicate to the QUICC to automatically retry the error cycle (case 5), or, if data is valid,
assert DSACKx (case 1).
is in error (case 3). This initiates exception processing for software handling of the con-
dition.
next clock cycle (case 4). This initiates exception processing for software handling of
the condition.
the next clock cycle (case 6). The memory controller can then correct the RAM prior
to or during the automatic retry.
2
3
4
5
6
1
DSACKx
DSACKx
DSACKx
DSACKx
DSACKx
DSACKx
Control
Signal
BERR
BERR
BERR
BERR
BERR
BERR
HALT
HALT
HALT
HALT
HALT
HALT
Table 4-8. DSACKx, BERR, and HALT Assertion Results
Asserted on Rising
NA/A
NA/A
A/S
A/S
NA
NA
NA
NA
NA
NA
NA
NA
Edge of State
N
A
A
A
A
A
A
Freescale Semiconductor, Inc.
For More Information On This Product,
N + 2
NA
NA
NA
NA
S
X
S
S
X
S
X
A
X
S
S
X
A
A
MC68360 USER’S MANUAL
Go to: www.freescale.com
Normal cycle terminate and continue.
Normal cycle terminate and halt; continue when HALT negated.
Terminate and take bus error exception, possibly deferred.
Terminate and take bus error exception, possibly deferred.
Terminate and retry when HALT negated.
Terminate and retry when HALT negated.
Result
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