EZ80190AZ050EG Zilog, EZ80190AZ050EG Datasheet - Page 92
![IC WEBSERVER 50MHZ XTEMP 100LQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
EZ80190AZ050EG
Manufacturer Part Number
EZ80190AZ050EG
Description
IC WEBSERVER 50MHZ XTEMP 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80190AZ050SG.pdf
(221 pages)
Specifications of EZ80190AZ050EG
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80190x
Core
eZ80
Data Bus Width
8 bit
Program Memory Type
ROMLess
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3865
EZ80190AZ050EG
EZ80190AZ050EG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EZ80190AZ050EG
Manufacturer:
TYCO
Quantity:
120
Company:
Part Number:
EZ80190AZ050EG
Manufacturer:
Zilog
Quantity:
70
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PS006614-1208
UART Scratch Pad Registers
Bit
Position
7
DCD
6
RI
5
DSR
4
CTS
3
DDCD
2
TERI
1
DDSR
0
DCTS
The UARTx_SPR registers, listed in
general-purpose Read/Write registers.
Value
0–1
0–1
0–1
0–1
0–1
0–1
0–1
0–1
Description
Data Carrier Detect
In NORMAL mode, this bit reflects the inverted state of the
DCDx input pin. In LOOP-BACK mode, this bit reflects the
value of the UARTx_MCTL[3] = OUT2.
Ring Indicator
In NORMAL mode, this bit reflects the inverted state of the RIx
input pin. In LOOP-BACK mode, this bit reflects the value of
the UARTx_MCTL[2] = OUT1.
Data Set Ready
In NORMAL mode, this bit reflects the inverted state of the
DSRx input pin. In LOOP-BACK mode, this bit reflects the
value of the UARTx_MCTL[0] = DTR.
Clear to Send
In NORMAL mode, this bit reflects the inverted state of the
CTSx input pin. In LOOP-BACK mode, this bit reflects the
value of the UARTx_MCTL[1] = RTS.
Delta Status Change of DCD
This bit is set to 1 whenever the DCDx pin changes state. This
bit is reset to 0 when the UARTx_MSR register is read.
Trailing Edge Change on RI
This bit is set to 1 whenever a falling edge is detected on the
RIx pin. This bit is reset to 0 when the UARTx_MSR register is
read.
Delta Status Change of DSR
This bit is set to 1 whenever the DSRx pin changes state. This
bit is reset to 0 when the UARTx_MSR register is read.
Delta Status Change of CTS
This bit is set to 1 whenever the CTSx pin changes state. This
bit is reset to 0 when the UARTx_MSR register is read.
Table 37
on page 83, can be used by the system as
Universal Asynchronous Receiver/Transmitter
Product Specification
eZ80190
82
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